Package Layout Design Engineer , Annapurna Labs - AI Silicon Packaging

Amazon • Cupertino, CA

1d

About The Position

Annapurna Labs (our organization within AWS) designs silicon and software that
accelerates innovation. Customers choose us to create cloud solutions that solve
challenges that were unimaginable a short time ago—even yesterday. Our custom
chips, accelerators, and software stacks enable us to take on technical
challenges that have never been seen before, and deliver results that help our
customers change the world.

We are seeking a Package Layout Design Engineer to join our hardware team and
contribute to the physical design of advanced IC packages for next-generation
machine learning and data center ASICs.
In this role, you will execute package layout tasks from floor planning through
tape out and manufacturing release, working closely with senior engineers,
SI/PI, thermal, and manufacturing teams to deliver production-ready designs that
meet performance, density, and reliability targets.

Requirements

• Bachelor's degree in Electrical Engineering or a related field
• 5+ years of experience in IC package layout and physical design
• Experience executing package designs from concept through tape out for multi-layer organic substrates or silicon interposers
• Hands-on experience with package layout tools such as Cadence APD/SiP, Synopsys IC Packaging, Mentor Xpedition, or equivalent
• Understanding of advanced packaging technologies: 2.5D/3D-IC, fan-out WLP, RDL, TSV, microbump, or silicon bridge interconnects
• Working knowledge of package design rules, DFM constraints, and physical verification methodologies (DRC, connectivity checks)
• Experience with bump map and ball map definition, escape routing strategies, and power/ground plane design
• Good communication skills with the ability to work effectively across design, SI/PI, and manufacturing teams

Nice To Haves

• MS with 3+ years in IC package layout and physical design
• Familiarity with substrate and interposer manufacturing processes, material properties, and their impact on design decisions
• Exposure to chiplet-based or heterogeneous integration packaging architectures
• Familiarity with package-level SI/PI concepts (impedance control, PDN layout, crosstalk-aware routing) sufficient to collaborate with SI/PI engineers
• Experience developing automation scripts (Python, TCL, Skill, Ravel) for layout tasks or design rule checks
• Exposure to working with OSAT partners on NPI builds or yield improvement efforts
• Familiarity with high-bandwidth memory (HBM) integration in advanced packaging contexts

Responsibilities

• Execute package layout tasks across the design cycle: die floor planning, bump/pad assignment, RDL routing, substrate design, verification, and tape out release.
• Implement physical designs for advanced packaging architectures including 2.5D interposer, 3D-IC, fan-out wafer-level packaging, and silicon bridge technologies (e.g., CoWoS, EMIB, or similar).
• Support package floorplan development considering die placement, bump maps, power/ground distribution, signal escape routing, and decoupling capacitor placement.
• Perform RDL and substrate routing for high-density interconnects including microbumps, C4 bumps, TSVs, microvias, and PTH vias across multi-layer organic substrates or silicon interposers.
• Support die-level RDL routing and bump planning in coordination with ASIC physical design teams to help co-optimize the die-package interface.
• Contribute to cross-level layout co-optimization across die RDL, interposer/substrate, and PCB levels under guidance from senior engineers.
• Assist in maintaining package stack-up definitions in collaboration with SI/PI and materials engineering teams.
• Run physical verification checks (DRC, connectivity, shorts/opens) and support design closure.
• Follow and help refine package design rules and guidelines, working with OSAT partners and foundries to ensure DFM compliance.
• Collaborate with SI/PI engineers to incorporate electrical constraints into the physical layout — impedance-controlled routing, power plane optimization, and critical net shielding.

Benefits

• health insurance (medical, dental, vision, prescription, Basic Life & AD&D insurance and option for Supplemental life plans, EAP, Mental Health Support, Medical Advice Line, Flexible Spending Accounts, Adoption and Surrogacy Reimbursement coverage)
• 401(k) matching
• paid time off
• parental leave

What This Job Offers

• Job Type: Full-time
• Career Level: Mid Level