Sr. Physical Design Verification Engineer, Annapurna Labs

Amazon • Cupertino, CA

1d • Onsite

About The Position

Annapurna Labs (our organization within AWS Utility Computing) designs silicon and software that accelerates innovation. Customers choose us to create cloud solutions that solve challenges that were unimaginable a short time ago—even yesterday. Our custom chips, accelerators, and software stacks enable us to take on technical challenges that have never been seen before, and deliver results that help our customers change the world.

Amazon Web Services provides a highly reliable, scalable, low-cost infrastructure platform in the cloud that powers hundreds of thousands of businesses in 190 countries around the world. We have data center locations in the U.S., Europe, Singapore, and Japan, and customers across all industries.

Custom SoCs (System on Chip) live at the heart of AWS Machine Learning servers. As a member of the Cloud-Scale Machine Learning Acceleration team you’ll be responsible for the design and optimization of Silicon and Hardware in our data centers including AWS Inferentia, Trainium Systems (our custom designed machine learning inference and training datacenter servers). Our success depends on our world-class server infrastructure; we’re handling massive scale and rapid integration of emergent technologies. We’re looking for an ASIC Physical Design Integration and Verification Engineer to join our backend team. The ideal candidate will be responsible for ensuring the quality and manufacturability of complex semiconductor designs through physical verification processes, and help us trail-blaze new technologies - Its still Day 1 here!

Requirements

• Experience in Python, Perl, or another scripting language
• BS + 10yrs or MS + 7yrs in EE/CS, or related field
• 5+ in physical verification for advanced technology nodes
• Expert knowledge of industry-standard physical verification tools (Calibre, IC Validator, PVS)
• Strong understanding of semiconductor manufacturing processes and design rules
• Proven track record of successful tape-outs
• Strong communication and collaboration abilities
• Design Flow Knowledge: Understanding of backend physical design flows (FC/Innovus)

Nice To Haves

• Experience with integration and verification in advanced nodes [5nm or below]
• Knowledge of custom and digital design flows
• Expertise with DFM (Design for Manufacturing) methodologies
• Expertise in reliability verification (ESD, EM, IR drop)
• Background in layout design or custom IC development

Responsibilities

• Drive full chip floorplan, integration and physical verification sign-off and closure
• Define, execute and optimize next-generation physical verification and integration methodologies using industry-standard EDA tools (Calibre, IC Validator)
• Perform DRC (Design Rule Checking), LVS (Layout vs. Schematic), PERC (Programmable Electrical Rule Check) verification, and Fill insertion
• Debug and resolve physical verification issues in collaboration with layout and design teams
• Interface with foundries for MT form, rule deck updates and violation waivers
• Develop and maintain verification runsets and methodologies
• Support technology file development and qualification
• Fine tune cloud infrastructure to improve compute and storage utilization for physical design work.
• Mentor junior engineers on physical verification methodologies and closure

Benefits

• health insurance (medical, dental, vision, prescription, Basic Life & AD&D insurance and option for Supplemental life plans, EAP, Mental Health Support, Medical Advice Line, Flexible Spending Accounts, Adoption and Surrogacy Reimbursement coverage)
• 401(k) matching
• paid time off
• parental leave

What This Job Offers

• Job Type: Full-time
• Career Level: Senior