Package Design Engineer - Up to Staff level

Qualcomm • San Diego, CA

10d • $154,000 - $252,800

About The Position

Qualcomm Data Center team is developing High performance, Energy efficient server solution for data center applications. We are looking for highly talented, innovative, teamwork-oriented individuals for our cutting-edge technology work!

Requirements

• Fundamental knowledge or proven experience in the following:
• Proficient in Cadence APD & SiP.
• Basic knowledge in high-speed IO interfaces and electromagnetic field.
• Knowledge of IC packaging structures, chip-package, and package-board interaction.
• Basic knowledge of electronic packaging process and typical failure modes preferred.

Nice To Haves

• Master's degree in electrical engineering, mechanical engineering, material science, or related fields with 5+ years of experience.
• Proven fundamentals in electrical, material, thermal, or mechanical engineering fields.
• Familiarity with various sophisticated package configurations and assembly/substrate technology (Flip chip BGA, 2.5D/3D Interposer, etc.).
• Experience in package design and proficiency in Cadence Allegro platform tools (PCB Editor, Advanced Package Designer, APD/SiP).
• Basic understanding of some SI/PI tools (XtractIM, PowerSI, HFSS, Q3D, etc.), package model extraction, S-parameters, and RLGC model.
• Basic knowledge of substrate manufacturing process, structure, design rules, and material properties.
• Proven understanding of high-speed interfaces, including DDR, PCIe, UCIE, etc.
• Experience with Calibre tool and package design reviews.
• Knowledge of high-speed layout constraints (crosstalk mitigation, differential pairs).
• Solid understanding of Design Rules Check and Design for Manufacturing.

Responsibilities

• Own and drive advanced package selection, new generation product package structure, and configuration optimization.
• Responsible for Package/SIP physical design and layout, optimization, DV, and tape out.
• Work with multi-functional teams to achieve optimized mechanical, electrical, and thermal performance for various types of chips.
• Implement the physical design of packages and modules for SoC.
• Interface and coordinate with multi-functional groups throughout Qualcomm on new product package/SiP feasibility analysis, design, and selection.
• Define and develop design verification and automation strategy to strengthen and streamline package design and release flows.
• Work multi-functionally to optimize package pin out.
• Ensure package design is optimized with SI/PI requirements.
• Drive methodology, innovations, and efficiency improvements in package design together with vendors and developers on feature development and bug resolution.
• Explore, evaluate, and develop new CAD tools, design, and verification flow.
• Partner with BU PD team to optimize chip Floorplan and bump placement and optimize the package size.

Benefits

• Competitive annual discretionary bonus program
• Opportunity for annual RSU grants
• Highly competitive benefits package designed to support your success at work, at home, and at play.

What This Job Offers

• Job Type: Full-time
• Career Level: Senior