NAND Design FE/BE Senior SD Engineer
About The Position
We are looking for an experienced Senior RTL Design Engineer with deep expertise in front-end and/or back-end digital logic design to help drive the development of next-generation SoC/SSD architectures. This role involves architecture definition, RTL design, synthesis, timing closure, and design verification support for complex digital subsystems. The ideal candidate will have a strong background in digital design, RTL development, and backend integration, particularly in storage or memory-related applications. In this role, you will be tasked to drive these 2 primary FE/BE objectives of Logic design:Front-End:-Help define logic HW / FW controller architecture for 3D NAND design. This involves deep-understanding of existing controller design and advancing its architecture for best die-size and power consumption. RTL design is in System Verilog and custom FW primarily in basic assembly language. You'll also be tasked to verify all timing closure of the designated blocksBack-End:-Help execute the advanced RTL-to-GDS process of the several large logic controller partitions of 3D NAND chip design. This involves synthesis, place-and-route, timing closure, post-r2g to schematic conversion on Virtuoso, and layout DRC. You'll also help drive the flow improvement from the existing DC/ICC2 flow to the more advanced Fusion Compiler flow. You'll be in charge of large periphery-level routing using Fusion-Compiler and porting back to Virtuoso via Lynx
Requirements
- MS with 7+ years or BS with 10+ years of experience in FE/BE design
- Expert knowledge of System-Verilog, Mem Controller architecture
- Expert in Synthesis, Place & Route, PrimeTime, and DRC
- Expert in DC/ICC2 and Fusion-Compiler tool set/env
- Strong knowledge of design PDK esp. stdcell
- Strong background in physical layout design and layout verification
- Solid Virtuoso schematic/layout environment
Responsibilities
- Help define logic HW / FW controller architecture for 3D NAND design
- Advance existing controller design for best die-size and power consumption
- RTL design in System Verilog and custom FW primarily in basic assembly language
- Verify all timing closure of the designated blocks
- Help execute the advanced RTL-to-GDS process of the several large logic controller partitions of 3D NAND chip design
- Synthesis, place-and-route, timing closure, post-r2g to schematic conversion on Virtuoso, and layout DRC
- Drive the flow improvement from the existing DC/ICC2 flow to the more advanced Fusion Compiler flow
- In charge of large periphery-level routing using Fusion-Compiler and porting back to Virtuoso via Lynx
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What This Job Offers
Job Type
Full-time
Career Level
Senior
