FE Design Engineer

Sandisk • Milpitas, CA

2d

About The Position

We are looking for experienced FE Tools Engineer with at least 10 years of hands-on experience with FE implementation tools. This role serves as the technical bridge between RTL design and back-end physical implementation. Synthesis Constraint Definition, Integration and Promotion Define, maintain, and validate project-level synthesis constraints (SDC). Integrate synthesis constraints from third-party IPs (e.g., PCIe PHY, memory controllers) into project synthesis constraints. Ensure third-party IP timing assumptions and constraints are correctly aligned with top-level design intent Resolve constraint conflicts between internal logic and external IPs SDC and STA experience for IP level timing constraint expertise. multi-clock domain timing relationships, definitions. mixed-signal interfaces. 3rd party IP knowledge (such as PCI-E, DDR, etc). Skew matching requirement and timing checks. Understanding the concepts of multi-power domains design and the impact on timing constraints. Help designers on complex timing violations (usually cross clock domain, set case analysis, MCP, etc). LINT, CDC, RDC support. ECO support.

Requirements

• Strong understanding of ASIC/SoC synthesis and timing methodologies
• Experience with SDC, UPF/CPF, and formal equivalence checking (LEC)
• Familiarity with third-party IP integration (e.g., PCIe, DDR, SerDes)
• Proficiency in industry-standard EDA tools for synthesis, STA, and formal verification
• Strong scripting skills (Tcl, Python)
• Solid communication skills for cross-team and vendor collaboration

Responsibilities

• Synthesis Constraint Definition, Integration and Promotion
• Define, maintain, and validate project-level synthesis constraints (SDC).
• Integrate synthesis constraints from third-party IPs (e.g., PCIe PHY, memory controllers) into project synthesis constraints.
• Ensure third-party IP timing assumptions and constraints are correctly aligned with top-level design intent
• Resolve constraint conflicts between internal logic and external IPs
• SDC and STA experience for IP level timing constraint expertise.
• multi-clock domain timing relationships, definitions.
• mixed-signal interfaces.
• 3rd party IP knowledge (such as PCI-E, DDR, etc).
• Skew matching requirement and timing checks.
• Understanding the concepts of multi-power domains design and the impact on timing constraints.
• Help designers on complex timing violations (usually cross clock domain, set case analysis, MCP, etc).
• LINT, CDC, RDC support.
• ECO support.

Benefits

• We offer a comprehensive package of benefits including paid vacation time; paid sick leave; medical/dental/vision insurance; life, accident and disability insurance; tax-advantaged flexible spending and health savings accounts; employee assistance program; other voluntary benefit programs such as supplemental life and AD&D, legal plan, pet insurance, critical illness, accident and hospital indemnity; tuition reimbursement; transit; the Applause Program, employee stock purchase plan, and the Sandisk's Savings 401(k) Plan.

What This Job Offers

• Job Type: Full-time
• Career Level: Mid Level
• Education Level: No Education Listed
• Number of Employees: 5,001-10,000 employees