MTS SoC DFT Engineer, HBM

Micron • Richardson, TX

1d

About The Position

Micron Technology, a world leader in memory and storage solutions, is seeking an MTS SoC DFT Engineer for its Heterogeneous Integration Group (HIG). This role focuses on developing High Bandwidth Memory (HBM) solutions for AI and ML applications, utilizing Through Silicon Via (TSV) technology to stack DRAM chips with a memory controller and logic chip. The goal is to improve memory density and bandwidth while delivering low power per bit solutions. The engineer will own design for test (DFT) solutions for complex HBM system-on-chip (SoC) base-die designs, ensuring manufacturability, quality, and successful silicon bring-up for current and future HBM generations. The team is inclusive and forward-thinking, working on technologies for virtual reality, neural networks, and next-generation computing.

Requirements

• Strong hands-on experience with SoC develop for test (DFT) architecture and implementation, including scan insertion, MBIST/LBIST concepts, boundary scan (JTAG), and ATPG.
• Experience working across full RTL-to-GDS SoC flows and collaborating with synthesis, static timing analysis (STA), and physical design teams.
• Proficiency using industry-standard EDA tools from Siemens, Synopsys, and/or Cadence for DFT and implementation.
• Bachelor’s degree in Electrical Engineering, Computer Engineering, or a related field, or equivalent practical experience.
• 10+ years of relevant experience in SoC design, DFT, or implementation for complex digital application-specific integrated circuits (ASICs) or SoCs.

Nice To Haves

• Experience with large, complex SoCs that integrate multiple intellectual property (IP) blocks and subsystems.
• Strong RTL debugging, design analysis, and problem-solving skills.
• Experience using scripting languages such as Python, Tcl, or Perl for flow automation.
• Familiarity with memory systems such as dynamic random-access memory (DRAM), high-bandwidth memory (HBM), and related JEDEC specifications.

Responsibilities

• Own SoC-level DFT structures and their implementation, including scan, MBIST, LBIST, JTAG, and test access architectures for HBM base-die builds.
• Define and drive DFT architecture early in the design cycle, ensuring alignment with SoC integration, floorplanning, timing, power, and physical design requirements.
• Implement and integrate DFT logic at block, subsystem, and full-chip levels, partnering with RTL design and SoC integration teams.
• Complete and sign off DFT flows, including linting, CDC checks, DFT rule checks, ATPG readiness, and coverage closure.
• Collaborate with physical design teams to optimize DFT solutions for placement, routing, timing closure, and DRC/LVS signoff.
• Work with verification, product engineering, test, probe, and manufacturing teams to ensure testability, diagnosability, and smooth pre-silicon debug and post-silicon bring-up.
• Partner with CAD and methodology teams to standardize and improve DFT flows, contribute to cross-group technical reviews, mentor engineers, and drive innovation for future HBM generations.
• Apply Gen-AI and Agentic-AI solutions to improve DFT workflows and methodologies.

Benefits

• Choice of medical, dental and vision plans
• Benefit programs that help protect your income if you are unable to work due to illness or injury
• Paid family leave
• Robust paid time-off program
• Paid holidays

What This Job Offers

• Job Type: Full-time
• Career Level: Senior