Mixed Signal Logic Design Engineer

Intel Corporation•San Jose, CA

2d•$122,440 - $232,190•Onsite

About The Position

Develops the logic design, register transfer level (RTL) coding, and simulation for mixed signal and/or highspeed IPs required to generate cell libraries, functional units, IP blocks, and subsystems for integration in full chip designs. Participates in the definition of architecture and microarchitecture features of the block being designed. Applies various strategies, tools, and methods for mixed signal designs including analog behavior modeling and circuit simulation to write RTL and optimize mixed signal logic to qualify the design to meet power, performance, area, and timing goals as well as design integrity for physical implementation. Reviews the verification plan and implementation to ensure design features are verified correctly and resolves and implements corrective measures for failing RTL tests to ensure correctness of features. Supports SoC customers to ensure high quality integration of the IP block.

Requirements

Bachelors with 4+ years of experience or master's with 3+ years of experience or PhD with 1+ years of experience in Computer Science or Computer Engineering or Electrical Engineering or related technical discipline
2+ years of experience with Proficiency in RTL design and coding using System Verilog and Verilog.
2+ years of experience with Expertise in mixed signal fundamentals, low-power design using UPF, and clock gating.
2+ years of experience with Deep understanding of digital and analog design principles, clock domain crossing, and power-performance tradeoffs.
2+ years of experience with Experience with hardware simulation tools and methodologies (VCS/Verdi).
Familiarity with IP environment and configuration management tools
Experience with Front End design tools for Lint, CDC, RDC, Voltage Domain Crossings, Synthesis, Low power design.

Nice To Haves

Demonstrated ability to debug complex logic designs, speed paths and validate system-level functionality.
Ability to collaborate across diverse teams, mentor junior engineers, and contribute to a dynamic team environment.
Strong problem-solving skills, disciplined execution, and a proactive mindset.
DDR Design domain knowledge with good hold on DFI/DDR/LPDDR protocols
VSCode GitHub CoPilot or any other AI experience.
Exposed to Formal Property Verification and Git version control
Ability to drive an optimal solution between analog and digital designs
Familiarity with pre-silicon and post-silicon validation.

Responsibilities

Develops the logic design, register transfer level (RTL) coding, and simulation for mixed signal and/or highspeed IPs.
Participates in the definition of architecture and microarchitecture features of the block being designed.
Applies various strategies, tools, and methods for mixed signal designs including analog behavior modeling and circuit simulation to write RTL and optimize mixed signal logic.
Qualifies the design to meet power, performance, area, and timing goals as well as design integrity for physical implementation.
Reviews the verification plan and implementation to ensure design features are verified correctly.
Resolves and implements corrective measures for failing RTL tests to ensure correctness of features.
Supports SoC customers to ensure high quality integration of the IP block.