Mixed Signal Design Engineer

CienaOttawa, ON
CA$90,600 - CA$144,800

About The Position

As the global leader in high-speed connectivity, Ciena is committed to a people-first approach. Our teams enjoy a culture focused on prioritizing a flexible work environment that empowers individual growth, well-being, and belonging. We’re a technology company that leads with our humanity—driving our business priorities alongside meaningful social, community, and societal impact. The Wavelogic family of products is widely used in Ciena's optical fiber transmission solutions and is one of the main contributors to Ciena's success in the telecommunications industry. Successful candidates will be joining a vibrant team with a proven track record of success over 30 years of evolution and revolution in the advancement of high-speed circuits used in broadband fiber-optic modems. This team pioneered the introduction of the world’s first high-speed DAC and ADC analog macros that ushered in the era of coherent fiber-optic product solutions.

Requirements

  • Electrical or computer engineering, computer science or other applicable scientific degree at the BEng/BSc, MEng/MSc, or PhD level
  • Design experience in the latest CMOS and BiCMOS technology
  • Proficiency with Cadence Virtuoso/Xcelium/AMS, Synopsys VCS/StarRC, Siemens Questa/Formal/Calibre/SymphonyAMS/AFS
  • Familiarity with SystemVerilog, VerilogAMS, VerilogA, Matlab/Simulink, C/C++, Python languages
  • Ability to work independently and collaboratively with team members
  • Skills of writing and presenting in English

Nice To Haves

  • Knowledge of UVM, Git, Gradle, Google Tests
  • Experience with the RF and Signal Integrity tools
  • DSP, digital, and analog design and modelling in high SerDes application
  • AI tools for automation

Responsibilities

  • Designing the high precision Sigma-Delta DAC and ADC for control and monitoring
  • Designing the SystemVerilog models for various analog macros
  • Designing the IBIS-AMS models for the high-speed DAC and ADC based SerDes IP running at 56Gbd, 112Gbd, 224Gbd, and 448Gbd
  • Creating Design Specification Document
  • Interacting with and providing support to the system team, analog team, the digital team, the DSP team, the signal integrity team, the hardware team, firmware team, and the analog lab bring-up team.

Benefits

  • medical, dental, and vision plans
  • participation in 401(K) (USA) & DCPP (Canada) with company matching
  • Employee Stock Purchase Program (ESPP)
  • Employee Assistance Program (EAP)
  • company-paid holidays
  • paid sick leave
  • vacation time
  • Paid Family Leave and other leaves of absence
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