Mixed Signal IC Layout Engineer
About The Position
Tenstorrent is seeking a Mixed Signal IC Layout Design Engineer to perform full-custom physical layout of analog and mixed-signal integrated circuits. This role involves transforming schematics into manufacturable layouts that meet stringent performance, power, area, and reliability targets in advanced FinFET processes. The focus is on creating high-quality, high-speed analog/mixed-signal blocks and integrating them into larger System-on-Chips (SoCs). This position is remote and can be based anywhere in the United States. Tenstorrent welcomes candidates at various experience levels, and the final level will be determined during the interview process.
Requirements
- Experienced analog/mixed-signal IC layout engineer with strong full-custom layout background on high-speed blocks (PLLs, VCOs, ADCs, DACs, LDOs, comparators, clock generators, high-speed I/Os).
- Proficient with Synopsys Custom Compiler or Cadence Virtuoso for custom layout.
- Proficient with Synopsys ICV or Siemens Calibre for physical verification (DRC, LVS, ERC, DFM, Antenna).
- Deep experience in CMOS/FinFET nodes (ideally TSMC or Samsung 12nm–2nm) with delivered silicon.
- Strong grasp of EM/IR, ESD, and latch-up in mixed-signal layouts.
- Detail-oriented and organized.
- Able to own complex blocks independently and collaborate effectively with circuit designers.
- Typically hold a BSEE (or equivalent experience) with ~10+ years in analog/mixed-signal layout.
Nice To Haves
- Contribute layout methodology and automation/scripts (Python, Tcl, SKILL, etc.) to improve team-wide quality and productivity.
Responsibilities
- Execute full-custom analog/mixed-signal layout for key blocks (PLLs, VCOs, ADCs, DACs, LDOs, bandgaps, comparators, clock generators, high-speed I/Os) from schematics to manufacturable layouts.
- Develop optimized block and top-level floorplans, placement, and routing that balance area, parasitics, matching, congestion, and integration into our D2D PHY.
- Apply best-known layout practices and optimize parasitics (R/C), coupling, IR drop, and electromigration to meet precision, noise, timing, and power goals while closing DRC, LVS, ERC, DFM, and Antenna.
- Support post-layout extraction and simulation.
- Contribute layout methodology and automation/scripts (Python, Tcl, SKILL, etc.) to improve team-wide quality and productivity.
Benefits
- Highly competitive compensation package
- Benefits
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What This Job Offers
Job Type
Full-time
Career Level
Mid Level
