Senior Mixed-Signal Lead to spearhead the architecture and design of high-performance clocking solutions, including PLLs, FLLs, and DLLs, for our next-generation silicon. In this leadership role, you will be responsible for the full lifecycle of analog timing IPs and post-silicon validation. The ideal candidate has 8+ years of experience in mixed-signal design with a specific focus on low-jitter, low-power frequency synthesis in advanced process nodes (N5, N3P). You will drive the trade-offs between analog and digital implementations of clocking circuits, ensuring seamless integration into large-scale SoCs. As a technical lead, you will manage external IP vendors, define internal design methodologies, and collaborate closely with Analog Design and Physical Design teams to mitigate noise coupling and power supply integrity issues. A deep understanding of jitter decomposition, phase noise analysis, and silicon bring-up is essential and Matlab, Arcsim experience is desired.
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Job Type
Full-time
Career Level
Senior