Methodology Engineer – Static RTL Verification

Advanced Micro Devices, Inc•San Jose, CA

About The Position

This role involves planning, developing, and maintaining AMD EDA tools focused on RTL static checks and supporting frameworks. These tools are used across AMD SoC teams to help ensure high‑quality RTL design. You are motivated by solving complex engineering problems and enjoy working with digital design, SystemVerilog, and static RTL checking methodologies. You collaborate effectively with engineers across teams and geographies and are comfortable communicating technical concepts with diverse partners. You approach problems analytically, take ownership of your work, and continuously build new skills.

Requirements

Demonstrated experience with RTL lint, CDC, low‑power static analysis, or related verification and design methodologies
Strong working knowledge of SystemVerilog and UPF
Proficiency in one or more scripting languages such as Python, Perl, Tcl, or shell
Experience debugging RTL issues and using static analysis tools
Familiarity with Linux environments; exposure to Windows is a plus
Working knowledge of Verilog, SystemVerilog, and/or VHDL
Experience with industry‑standard static and low‑power vendor tools is beneficial
Bachelor’s or master’s degree in Electronics Engineering, Computer Engineering, or equivalent practical experience

Responsibilities

Lead and contribute to the development and qualification of a static RTL quality‑checking tool, with a focus on production‑ready quality and scalability
Collaborate closely with RTL, verification, and methodology teams to integrate the tool into frontend and verification workflows
Design and execute tool‑qualification regressions across complex AMD SoC designs, ensuring correctness across use cases and configurations
Build and maintain automation, infrastructure, and reporting to improve regression efficiency and debuggability
Support frontend, static, and power‑aware design flows, including SystemVerilog, UPF, SDC timing constraints, and static analysis tools (e.g., Lint, CDC, RDC, LEC, VCLP/CLP, Fishtail‑TCM)