Memory Electrical Validation Engineer

Intel Corporation•Hillsboro, OR

6d•$190,610 - $269,100•Hybrid

About The Position

The world is transforming - and so is Intel. Intel is a company of bold and curious inventors and problem solvers who create some of the most astounding technology advancements and experiences in the world. With a legacy of relentless innovation and a commitment to bring smart, connected devices to every person on Earth, our diverse and brilliant teams are continually searching for tomorrow's technology and revel in the challenge that changing the world for the better brings. We work every single day to design and manufacture silicon products that empower people's digital lives. Come join us and do something wonderful. Note: This role requires regular onsite presence to fulfill essential job responsibilities. Defines electrical validation strategy for memory IO interfaces to achieve optimized electrical performance and meet product production goals. Validates circuit analog performance, electrical signal integrity compliance to industry standard specifications, and system level margin for stable operation and production target prediction. Defines MRC (Memory Reference Code) requirements for validation and margin optimization and analyzes, validates, debugs, and optimizes MRC steps and values to optimize margins and quality. Conducts and participates in multidisciplinary research in the design, development, testing, validation, and utilization of memory IO and mixed signal architectures inclusive of industry standard datacom applications and custom Intel interfaces. Develops procedures, analysis, and designs for validation, validation infrastructure, and systems margin validation. Analyzes internal and external customer returns with emphasis on improving yields and driving test escape closure. Applies and uses independent evaluation to select components and equipment based on analysis of specifications, performance, and reliability. Performs debug to identify root causes and resolves all functional and triage failures for electrical issues. Tests interactions between various electrical design features using validation infrastructure. Applies understanding of DFT and DFM to collaborate with architecture, design, and presilicon verification teams to ensure capability to validate and test IO architecture implementations. Prepares validation specifications, evaluates IP, and generates test reports. Ensures products conform to standards and specifications.

Requirements

Bachelors or Master's degree in electrical engineering or physics or computer engineering or another relevant field
5+ years of experience in Memory/DDR technology
5+ years of hands-on validation and debug experience at system level and memory interfaces
5+ years of experience with industry-standard JEDEC memory protocols and test methodologies

Nice To Haves

Understanding platform level signal integrity and power integrity technologies a definite asset
Experience with validation of high-speed I/O interfaces, including understanding of Tx, Rx, PLL, DLL, Clocking, and Equalization
Knowledge of computer architecture (CPU, DDR Memory technologies) and software/firmware architecture (bios, firmware debug experience)
Hands-on experience of validation & debug using tools such as Oscilloscopes, Signal generators, BERT, and Logic analyzers
Familiarity of Server/Xeon Memory RAS features
Python scripting/programming skills
Must be a self-starter and be able to independently drive tasks to completion
In-depth knowledge of DRAM, Memory Controller and DDRIO/PHY architectures and design/validation concepts
Familiarity with Memory Reference Code (MRC), DDR training algorithms
Working knowledge of high-speed analog and digital circuits of IO

Responsibilities

Defines electrical validation strategy for memory IO interfaces to achieve optimized electrical performance and meet product production goals.
Validates circuit analog performance, electrical signal integrity compliance to industry standard specifications, and system level margin for stable operation and production target prediction.
Defines MRC (Memory Reference Code) requirements for validation and margin optimization and analyzes, validates, debugs, and optimizes MRC steps and values to optimize margins and quality.
Conducts and participates in multidisciplinary research in the design, development, testing, validation, and utilization of memory IO and mixed signal architectures inclusive of industry standard datacom applications and custom Intel interfaces.
Develops procedures, analysis, and designs for validation, validation infrastructure, and systems margin validation.
Analyzes internal and external customer returns with emphasis on improving yields and driving test escape closure.
Applies and uses independent evaluation to select components and equipment based on analysis of specifications, performance, and reliability.
Performs debug to identify root causes and resolves all functional and triage failures for electrical issues.
Tests interactions between various electrical design features using validation infrastructure.
Applies understanding of DFT and DFM to collaborate with architecture, design, and presilicon verification teams to ensure capability to validate and test IO architecture implementations.
Prepares validation specifications, evaluates IP, and generates test reports. Ensures products conform to standards and specifications.