Member of Technical Staff — Inference-Multi-Hardware

RadixArk•Palo Alto, CA

14h•$200,000 - $400,000

About The Position

RadixArk is seeking a Member of Technical Staff to push the limits of performance for frontier AI systems across multiple hardware platforms. The role brings up, optimizes, and maintains SGLang, Miles, and RadixArk’s infrastructure stack across NVIDIA and AMD GPUs, Google TPUs, modern server CPUs, and emerging AI accelerators. It involves porting kernels and runtimes to unfamiliar hardware and designing abstractions that keep a shared codebase performant across platforms. The engineer will work directly with silicon and vendor partners, often on pre-release platforms with immature tooling. The work spans new hardware architectures, compiler behavior, memory hierarchies, and collective communication capabilities, and requires quickly learning new architectures while applying strong performance-engineering skills. RadixArk is an infrastructure-first company building open systems for AI inference and training. It created SGLang and developed Miles, and works with Nvidia, Google, and frontier AI labs. The expected annual salary range is $200,000–$400,000 USD plus equity. RadixArk is an Equal Opportunity Employer.

Requirements

At least 4 years of experience in systems, performance, or ML infrastructure engineering.
Deep expertise in at least one accelerator programming model, such as CUDA, ROCm/HIP, Pallas/XLA, Triton, or a vendor SDK, and demonstrated ability to learn new models quickly.
Strong understanding of accelerator architecture, including memory hierarchy, bandwidth limits, occupancy, and their tradeoffs.
Experience writing or optimizing high-performance kernels for ML workloads.
Experience with distributed execution and communication libraries such as NCCL, RCCL, MPI, or equivalents.
Proficiency in C++ and Python.
Strong system-level debugging and profiling skills, including on platforms with incomplete or unreliable tooling.
Track record of performance work shipped into production.

Nice To Haves

Experience bringing up ML workloads on new silicon.
Hands-on depth in more than one vendor ecosystem.
Experience with compiler stacks such as XLA, MLIR, TVM, or Triton, or building compiler passes and IR transformations.
Experience designing hardware abstraction layers or portable kernel interfaces.
Quantization and mixed-precision work across differing numeric formats and hardware support levels.
Experience with distributed inference systems such as SGLang or vLLM, or training/RL frameworks such as Miles, Megatron, veRL, or TorchTitan.
CPU inference optimization, including AVX-512/AMX, oneDNN, or NUMA-aware execution.
Experience optimizing collective communication at scale or scaling workloads to 1,000+ accelerators.
Contributions to kernel, compiler, or ML systems open source.
Direct collaboration with silicon vendors or cloud partners on technical evaluations.
Background in HPC or other performance-critical systems.

Responsibilities

Bring up RadixArk’s inference and training systems on new accelerator platforms and drive them to competitive performance.
Design hardware abstractions that keep a single codebase performant across vendors without forking.
Port and optimize kernels across programming models and memory architectures.
Build cross-platform benchmarking, profiling, and regression detection so performance claims hold up on every target.
Debug numerical divergence and correctness gaps between platforms.
Work with vendor engineering teams on pre-release hardware, compiler and driver issues, and roadmap feedback.
Partner with kernel, runtime, distributed systems, and product engineers to deliver end-to-end performance improvements.
Serve as the internal source of truth on the strengths and capabilities of each platform.
Contribute hardware-specific optimizations, benchmarks, and portability work to open-source SGLang and Miles.