Member of Technical Staff, GPU Compiler

San Francisco Tensor Company•San Francisco, CA

18h•Onsite

About The Position

SF Tensor is hiring a Member of Technical Staff for GPU Compiler Engineering to build and extend its search-based GPU compiler. The role spans the compiler pipeline end to end, including StableHLO ingestion, MLIR dialects and passes, backend code generation, and executable GPU and host binaries. The compiler searches a wide space of program transformations and verifies correctness at the end, enabling aggressive optimization while guaranteeing the result. The work includes contributing to a custom LLVM backend that emits NVIDIA cubins directly, without ptxas, and developing comparable backend capabilities for AMD, TPU, and Trainium targets. The compiler supports production workloads across training and inference, and the role includes close collaboration with research teams and customer workloads to identify and implement impactful optimizations. SF Tensor describes its team as small and working at frontier scale, with most work taking place in person at its San Francisco office.

Requirements

Deep experience with compiler infrastructure such as LLVM, MLIR, or similar.
Strong background in GPU architecture and low-level optimization, such as CUDA or ROCm.
Hands-on experience with at least one GPU instruction set, such as PTX/SASS, GCN/RDNA assembly, or another GPU ISA.
Familiarity with ML compiler stacks such as XLA, TVM, Triton, or torch.compiler.
Solid systems programming skills in C++ and/or Rust.
A proven track record of building production-grade compiler infrastructure.

Nice To Haves

Experience in autotuning or search-based optimization.
Background in formal verification, proof assistants, or SMT solvers.
Experience writing or maintaining an LLVM backend.
Background in distributed systems or multi-device compilation.
Contributions to open-source compiler projects.
Familiarity with large-scale training infrastructure.
Experience with (Stable)HLO.

Responsibilities

Build and extend MLIR dialects and passes to optimize training and inference workloads.
Work on the LLVM backend, including instruction selection, scheduling, register allocation, and direct cubin emission, and develop equivalent capabilities for AMD, TPU, and Trainium targets.
Expand search-based compiler infrastructure, including agent- and reinforcement-learning-driven program search and formal correctness proofs.
Implement classic compiler optimizations for large-scale training.
Create hybrid code-generation paths for cases where direct MLIR lowering is not practical.
Own testing, benchmarking, and performance-regression systems, including bit-identical hardware models.
Work closely with the research team and customer workloads to identify important optimization opportunities.