Member of Technical Staff, ASIC Design

Netpreme•Santa Clara, CA

7d•Onsite

About The Position

Netpreme is building a full-stack solution to help AI memory scale independently of AI compute. Its work spans a proprietary memory management framework at the XPU kernel and OS levels and X-Mem™, a Memory Processing Unit (MPU) silicon product. The company is based in Cambridge, Massachusetts, and Santa Clara, California. The Member of Technical Staff, ASIC Design role is part of the Silicon Design Team and is responsible for RTL design of IPs, subsystems, and SoCs supporting Netpreme's silicon roadmap. The role calls for technical leadership in IP and SoC microarchitecture specifications and design methodologies, as well as guiding optimization to meet performance, power, and area goals. The role works closely with architecture, verification, physical design, firmware, DFT, and post-silicon teams, and interfaces with external IP vendors, foundries, and EDA tool providers. This is an onsite role at either the Santa Clara, California, or Boston, Massachusetts office. The position is focused on advanced ASIC design flows and delivery in the AI and data center space, including memory acceleration.

Requirements

Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
At least 5 years of ASIC/SoC digital design experience.
Strong leadership, communication, team-building, and stakeholder-management skills.
Strong knowledge of the full ASIC/SoC development cycle, from microarchitecture development through tape-out in advanced process technologies.
Expertise in microarchitecture development, RTL coding in Verilog/SystemVerilog, synthesis, STA/timing closure, physical design, and verification methodologies.
Hands-on design experience with one or more industry standards or protocol stacks, such as Ethernet, UCIe, or UALink.
Demonstrated ability to optimize designs for power, performance, and area and integrate major subsystems such as interconnect, I/O, and memory.
Proficiency with front-end development tools and methodologies, and scripting for automation and flow integration.

Nice To Haves

Design and tape-out experience with an advanced silicon device.
PhD in Electrical Engineering, Computer Engineering, or a related field.
Experience managing relationships with external design partners, IP vendors, and foundries.
Knowledge of Design-For-Testability, post-silicon debug and validation, or manufacturing test.

Responsibilities

Design RTL for IPs, subsystems, and SoCs supporting Netpreme's silicon roadmap.
Provide technical leadership in defining IP/SoC microarchitecture specifications and design methodologies.
Conduct design reviews to ensure adherence to best practices.
Guide design optimization to meet aggressive performance, power, and area goals using advanced architectural and design techniques.
Coordinate with architecture, verification, physical design, firmware, DFT, and post-silicon teams to ensure system-level functionality.
Work with external IP vendors, foundries, and EDA tool providers to address dependencies and roadblocks in support of team deliverables.
Coordinate across projects, manage risks and escalations, and work within tight schedules and budget constraints.

Benefits

Competitive salary with performance-based bonus and early-stage equity grant.
100% employer-paid health, dental, and vision coverage for employees and dependents.
401(k) match with immediate vesting and access to financial advisors.
100% employer-paid life, disability, and AD&D insurance.
Fitness stipend and wellness and mental health perks.
20 vacation days and 15 company holidays, including 3 floating days.
Daily lunch stipend.
Enterprise-level Claude and ChatGPT access with a generous token budget.
Well-equipped offices with on-site parking and EV charging; Santa Clara also has an on-site fitness center, and the Cambridge office offers nearby gym discounts.
Visa sponsorship and relocation assistance to an office hub.
Collaborative, continuous-learning environment.