Mechanical Engineering Manager

Teradyne•San Jose, CA

1d•$160,000 - $256,100•Onsite

About The Position

The Memory Test Division is seeking a technically strong, highly motivated Engineering Manager to lead a team focused on interface development and signal delivery for high-performance memory test platforms. This team is responsible for designing and optimizing the critical interconnects that enable clean, reliable, high-speed signaling to advanced memory devices. This position is based in San Jose, CA, operating within a fast-paced, multi-site engineering environment. You will report to the director and collaborate closely with teams across signal integrity, hardware design, mechanical engineering, and system architecture.

Requirements

Bachelor’s degree in Electrical Engineering, Mechanical Engineering, or related field.
8+ years of experience in electrical, mechanical, or electromechanical design within semiconductor equipment or high-speed hardware systems.
Demonstrated expertise in signal delivery, interconnect design, high-speed routing, or interface hardware development.
Strong background in design optimization, materials evaluation, and process improvements.
Proven ability to manage external design partners or contract engineering resources.
Excellent communication skills—oral, written, and presentation.
Broad technical fluency across hardware, software, mechanical, thermal, and system-level domains.
Deep understanding of the development lifecycle for electro-mechanical products.

Nice To Haves

Some travel overseas may be required – expect once per year.

Responsibilities

Direct engineering activities related to memory-test interface hardware, including load boards, probe interfaces, connectors, cabling systems, and other signal delivery.
Manage department budgets, staffing, personnel development, and recruitment for the interface team.
Lead a multidisciplinary team specializing in signal integrity, interconnect design and validation, materials, and electromechanical integration.
Build and execute a roadmap for interface improvements aligned with memory-test performance, reliability, and manufacturability targets.
Establish KPIs for signal quality, interface reliability, and test-system performance; report progress to senior leadership.
Collaborate with suppliers and external engineering partners to develop signal delivery solutions and interconnect.
Promote a culture of engineering rigor, signal-integrity awareness, and continuous improvement across the Memory Test Division.