Low Power ASIC Engineer - New College Grad 2027

NVIDIA•Santa Clara, CA

1d•$100,000 - $189,750

About The Position

NVIDIA is seeking a Low Power Design/Verification ASIC Engineer for new college graduates. The role involves contributing to the research and development of energy-efficient GPU and SOC architectures, focusing on innovative ways to improve performance per watt. The successful candidate will join the Low Power DV team to develop state-of-the-art GPUs for AI, Automotive, GeForce, and Mobile products.

Requirements

Recently completed a BS, MS or PhD in Electrical or Computer Engineering, or equivalent experience.
Understanding of low power design techniques such as multi VT, Clock gating, Power gating, Block Activity Power, and Dynamic Voltage-Frequency Scaling (DVFS).
Good understanding of processor architecture (GPU is a plus), and related power management design/DV techniques.
Experience with Incisive Low-Power or Synopsys VCS NLP.
Strong debug skills and experience with Verdi.
Fluent in Verilog, SystemVerilog, and understanding of UVM.

Nice To Haves

Prior knowledge of Low Power Architecture, Low Power CV, and deep learning.
Good understanding of power intent in UPF format.
A strong background in Low Power architectures or verification.
Scripting abilities in Python or PERL.
Knowledge of C or C++.
Experience writing or maintaining scripts or Makefiles that build the simulation program.

Responsibilities

Working closely with Low Power Architecture, Design, and Software teams to understand next-generation features.
Architecting and developing testbench, infrastructure, and testplans to verify various power management solutions for NVIDIA products.
Bringing creative ideas to improve power-aware DV methodologies and influencing EDA vendors to enhance simulation and debug efficiencies.