Lead Systems Architect

Axiado•San Jose, CA

5d•$210,000 - $260,000•Onsite

About The Position

As a Lead System Architect at Axiado, you will define the end-to-end architecture bridging silicon (ASIC/SoC), board-level hardware platforms, and low-level system software/firmware. Leveraging your deep expertise in the server and infrastructure industry, you will translate customer requirements into detailed technical specifications. This high-impact role requires navigating complex hardware/software tradeoffs while collaborating closely with Axiado’s engineering teams, customers, standards organizations and ecosystem partners.

Requirements

10+ years of dedicated system architecture experience spanning SoC design, board development, and software stacks.
Proven track record of engineering and architectural success within the server, data center, or enterprise infrastructure industry.
Demonstrated ability to independently produce and maintain highly detailed, production-grade technical specifications.
Excellent communication and presentation skills, with comfort interfacing directly with sophisticated enterprise customers and technical stakeholders.
B.S., M.S., or Ph.D. in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
Deep knowledge of SoC design flows, interconnects, and interfaces (PCIe, Ethernet, DRAM, USB).
Hands-on experience with hardware platform design, schematic capture, and lab bring-up tools (oscilloscopes, logic analyzers).
Clear understanding of embedded firmware, RTOS, Linux device drivers, and low-level C/C++ programming.
10+ years of hardware engineering experience with a leadership track record in server, data center, or semiconductor ecosystems.
Proven history of taking complex board designs to high-volume production with excellent yields and resolving field RMA issues.
Deep, continuous experience with circuit design, schematic capture, laboratory equipment, and platform troubleshooting.
Strong knowledge of OCP DC-SCM standard solutions (DC-SCI interface, form factors) and a solid network across hyperscaler and OEM partners.
Demonstrated capability to execute rapid hardware redesigns, footprint compatibility strategies, and alternative component sourcing.
Expert familiarity with Cadence OrCAD/Allegro and server interfaces (PCIe, USB, I2C, SMBus, SPI, UART, USB, MCTP, eSPI, LTPI).
Solid understanding of modern CPU/GPU architectures and the Linux environment (including Python or Bash scripting).
Exceptional verbal and written communication skills to articulate hardware-anchored security and supply chain strategy to enterprise stakeholders.

Nice To Haves

Active participation in open infrastructure communities like the Open Compute Project (OCP).
Deep understanding of hardware security concepts (cryptographic accelerators, HSM, TPM, Side-Channel attack mitigations).
Experience with BMC firmware architecture (OpenBMC) and server management interfaces (MCTP, NVMe-MI, LTPI).

Responsibilities

Own and author comprehensive, unambiguous system architecture specifications, micro-architectural specs, and/or platform requirement documents.
Define rigorous system-level hardware/software partition boundaries and map out register-level interfaces for hardware blocks and low-level software stacks.
Drive micro-architecture specifications for high-security, AI-driven SoCs, including on-chip interconnects (AXI/AHB), memory hierarchies, and standard I/O interfaces (PCIe, Ethernet, SPI, eSPI, I3C, LTPI).
Serve as a primary technical point of contact for enterprise and hyperscaler customers to gather, analyze, and scope their next-generation platform security needs.
Present Axiado’s system architecture roadmap and technical whitepapers to strategic customers, steering-level partners, and standards committees.
Align Axiado’s technology with modern server deployment topologies and open-source standards (such as OCP DC-SCM / DC-SCI).
Architect platform-level designs optimized for enterprise server motherboards, baseboard management systems, and cloud data center environments.
Guide hardware and SI/PI engineers on signal integrity, power delivery networks, and thermal/mechanical constraints for modular server building blocks.
Specify secure platform boot flows, Root-of-Trust (RoT) architecture, and Platform Firmware Resiliency (PFR) frameworks.
Collaborate with firmware teams to define interfaces for BMC stacks (OpenBMC), Linux kernels, device drivers, and platform management protocols (MCTP, PLDM, Redfish).