Lead Software Engineer - HYBRID

The Structures Company•Phoenix, AZ

1d•Hybrid

About The Position

The Lead Software Engineer builds tooling and processes for system-on-chip (SoC) performance monitoring. The role monitors usage, throughput, and traffic collisions through L2/L3 cache and the network-on-chip or communication fabric between on-die elements, and characterizes limits for bandwidth allocation, QoS values, channel priorities, and related technologies. The engineer develops tools to monitor last-level cache occupancy, memory-controller bandwidth utilization, and inter-core interference using Intel PMU/uncore counters. The role characterizes worst-case latency effects from cache and fabric contention and establishes QoS and bandwidth-allocation limits for mixed-criticality workloads. It also creates automated performance-monitoring infrastructure for Intel Xeon/Tiger Lake platforms to track cache misses, memory traffic, and QoS effectiveness. The position designs, modifies, develops, writes, and implements software applications; supports and installs software applications or operating systems; and participates in test review, analysis, witnessing, and certification. This is a six-month contract with potential for extension, based in Phoenix, Arizona, with a hybrid work arrangement and first-shift hours. Pay is $140 per hour.

Requirements

Must be a U.S. Person as defined under ITAR regulations.
8+ years of SoC analysis experience associated with building tooling or processes around performance monitoring.
Experience monitoring traffic usage, throughput, and collisions through L2/L3 cache and network-on-chip or communication fabric between on-die elements.
Ability to characterize and establish limits for bandwidth allocation, QoS values, channel priorities, and similar technologies.
Experience with Intel Tiger Lake, Ice Lake, or Alder Lake chips.
AC20-193 certification experience.
Experience developing tools to monitor LLC occupancy, memory-controller bandwidth utilization, and inter-core interference using Intel PMU/uncore counters.
Experience characterizing worst-case latency effects of cache and fabric contention and establishing QoS/bandwidth-allocation limits.
Experience creating automated performance-monitoring infrastructure for Intel Xeon/Tiger Lake platforms to track cache misses, memory traffic, and QoS effectiveness.
Bachelor's degree in a related area and 6–8 years of experience in the field.

Responsibilities

Build tooling and processes for SoC performance monitoring.
Monitor usage, throughput, and traffic collisions through L2/L3 cache and the network-on-chip or communication fabric between on-die elements.
Characterize and establish limits for bandwidth allocation, QoS values, channel priorities, and related technologies.
Develop tools to monitor LLC occupancy, memory-controller bandwidth utilization, and inter-core interference using Intel PMU/uncore counters.
Characterize worst-case latency effects of cache and fabric contention and establish QoS and bandwidth-allocation limits for mixed-criticality workloads.
Create automated performance-monitoring infrastructure for Intel Xeon/Tiger Lake platforms to track cache misses, memory traffic, and QoS effectiveness.
Design, modify, develop, write, and implement software programming applications.
Support and install software applications or operating systems.
Participate in test review, analysis, witnessing, and certification.