Lead Product Engineer

Cadence Design Systems • San Jose, CA

2d • $119,000 - $221,000

About The Position

Cadence is seeking a High-performance and Power-Critical CPU and/or GPU Implementation and Methodology Engineer to work on implementation and methodology challenges. The role covers full-chip and block-level implementation from RTL to signoff, including place-and-route, timing closure, physical verification, power analysis, and optimization. The engineer will develop scripts, utilities, and methodologies to improve productivity and design quality, and collaborate with architecture, RTL, verification, methodology, and CAD teams.

Requirements

• Strong understanding of physical design fundamentals, including floorplanning, placement, clock tree synthesis, routing, timing analysis, signal integrity, IR drop, and electromigration.
• Experience with timing-closure methodologies for setup, hold, power, and area optimization.
• Familiarity with low-power implementation techniques, including UPF/CPF, power gating, multi-voltage designs, clock gating, and leakage optimization.
• Ability to develop scripts, utilities, and methodologies to improve productivity and design quality.
• Familiarity with industry-standard implementation and signoff tools.
• Strong debugging and problem-solving skills, including the ability to analyze complex design issues and drive them to resolution.
• Good communication skills and ability to work effectively with cross-functional teams, including architecture, RTL, verification, methodology, and CAD teams.

Nice To Haves

• Prior experience with Python, Tcl, Perl, Shell, or other programming or scripting languages.
• Exposure to machine learning and AI-assisted optimization techniques.
• Understanding of advanced technology nodes (5nm and below) and related challenges, including congestion, variability, power integrity, and manufacturability.
• Experience with data analytics, design-space exploration, or AI-driven optimization frameworks for improving PPA and productivity.
• Experience in PPA optimization, design convergence, benchmarking, methodology development, and large-scale CPU/GPU implementation.

Responsibilities

• Perform full-chip and block-level implementation from RTL to signoff, including place-and-route, timing closure, physical verification, power analysis, and optimization.
• Apply timing-closure methodologies to optimize setup, hold, power, and area.
• Develop scripts, utilities, and methodologies to improve productivity and design quality.
• Debug complex design issues and drive them to resolution.
• Work effectively with cross-functional architecture, RTL, verification, methodology, and CAD teams.

Benefits

• Paid vacation
• Paid holidays
• 401(k) plan with employer match
• Employee stock purchase plan
• Medical, dental, and vision plan options
• Potential incentive compensation, including bonus and equity

What This Job Offers

• Job Type: Full-time
• Career Level: Senior
• Education Level: No Education Listed