Lead Product Engineer

Cadence Systems • San Jose, CA

1d

About The Position

Cadence is seeking a Lead Product Engineer for high-performance and power-critical CPU and/or GPU implementation and methodology engineering. The role covers full-chip and block-level implementation from RTL through signoff, including place-and-route, timing closure, physical verification, power analysis, and optimization. The engineer will apply physical design and low-power implementation techniques, develop automation and methodologies, and collaborate with cross-functional teams to resolve complex design issues and improve design quality, PPA, and productivity.

Requirements

• Strong understanding of physical design fundamentals, including floorplanning, placement, clock tree synthesis, routing, timing analysis, signal integrity, IR drop, and electromigration.
• Experience with timing-closure methodologies for setup, hold, power, and area optimization.
• Familiarity with low-power implementation techniques, including UPF/CPF, power gating, multi-voltage designs, clock gating, and leakage optimization.
• Ability to develop scripts, utilities, and methodologies to improve productivity and design quality.
• Strong debugging and problem-solving skills, including the ability to analyze complex design issues and drive them to resolution.
• Good communication skills and ability to work effectively with cross-functional teams.

Nice To Haves

• Experience with Python, Tcl, Perl, Shell, or other programming or scripting languages.
• Exposure to machine learning and AI-assisted optimization techniques.
• Familiarity with industry-standard implementation and signoff tools.
• Understanding of advanced technology nodes (5nm and below) and related challenges, including congestion, variability, power integrity, and manufacturability.
• Experience with data analytics, design-space exploration, or AI-driven optimization frameworks for improving PPA and productivity.
• Experience in PPA optimization, design convergence, benchmarking, methodology development, and large-scale CPU/GPU implementation.

Responsibilities

• Perform full-chip and block-level implementation from RTL to signoff, including place-and-route, timing closure, physical verification, power analysis, and optimization.
• Apply physical design fundamentals across floorplanning, placement, clock tree synthesis, routing, timing analysis, signal integrity, IR drop, and electromigration.
• Use timing-closure methodologies to optimize setup, hold, power, and area.
• Apply low-power implementation techniques, including UPF/CPF, power gating, multi-voltage designs, clock gating, and leakage optimization.
• Develop scripts, utilities, and methodologies to improve productivity and design quality.
• Debug complex design issues and drive them to resolution.
• Work with architecture, RTL, verification, methodology, and CAD teams.
• Contribute to PPA optimization, design convergence, benchmarking, methodology development, and large-scale CPU/GPU implementation.

Benefits

• Paid vacation
• Paid holidays
• 401(k) plan with employer match
• Employee stock purchase plan
• Medical, dental, and vision plan options
• Potential eligibility for incentive compensation, including bonus and equity

What This Job Offers

• Job Type: Full-time
• Career Level: Senior
• Education Level: No Education Listed