Lead Physical Design Engineer, Amazon Leo

Amazon • San Diego, CA

1d

About The Position

Amazon Leo is an initiative to launch a constellation of Low Earth Orbit satellites that will provide low-latency, high-speed broadband connectivity to unserved and underserved communities around the world.

Lead physical design activities for the Modem SOC. Interface and select 3rd party physical design vendor. Manage execution of physical design work. Close the feedback loop with RTL team based on physical design considerations. Implement complex designs in the targeted technology node.

Be part of Amazon LEO’s sub-team responsible for defining and implementing the digital chip SOCs for communications via Low Earth Orbit satellites and Amazon gateways. This is a unique opportunity to define the highest quality wireless solution with few legacy constraints. The team works with customer requirements and wireless system teams to define modems, high-speed interfaces, embedded processors, and DSP solutions in latest CMOS generation technologies.

Requirements

• 8+ years of ASIC implementation, synthesis, STA and physical design in deep sub-micron nodes (16nm or smaller) experience
• 8+ years of digital design in communication systems experience
• 8+ years of wireless communications systems and implementation experience
• Bachelor's degree in Electrical Engineering or a related field
• Bachelor's degree in Electrical Engineering/Communications Engineering, or experience designing digital communication systems
• Knowledge of implementing chips with multiple power islands and power gating
• Knowledge of serial protocols including SPI, I2C, I3C, and UART
• Experience low power design techniques
• Due to applicable export control laws and regulations, candidates must be a U.S. citizen or national, U.S. permanent resident (i.e., current Green Card holder), or lawfully admitted into the U.S. as a refugee or granted asylum.

Nice To Haves

• Master's degree or Ph.D. degree in Electrical Engineering or related field
• Experience with modern ASIC/FPGA design and verification tools
• Experience with SOC bring-up and post-silicon validation

Responsibilities

• Work closely with Architects, and RTL Designers to facilitate PPA analysis for technology node selection.
• Review and analyze technology specific 3rd party IP blocks for performance, supported collateral, and other KPI
• Review and analyze current and future 3rd party physical design teams to ensure high quality partnership.
• Review and analyze DFT coverage to ensure project and product requirements are met.
• Work closely with Architects and Designers to identify performance limits and improvements.
• Interface with the current 3rd party physical design team. Audit and improve existing checklists and flows.
• Build world class physical design capability through mentoring and hiring. This team will be capable of taking a design through floorplanning all the way to chip finishing.

Benefits

• health insurance (medical, dental, vision, prescription, Basic Life & AD&D insurance and option for Supplemental life plans, EAP, Mental Health Support, Medical Advice Line, Flexible Spending Accounts, Adoption and Surrogacy Reimbursement coverage)
• 401(k) matching
• paid time off
• parental leave

What This Job Offers

• Job Type: Full-time
• Career Level: Mid Level