Lead Photonics Designer Engineer - III/V Components

Salience Labs • San Francisco, CA

35d • Onsite

About The Position

Salience Labs is building an industry-defining approach to optical circuit switching for AI infrastructure, engineered for real latency reduction and cost savings. We're moving towards real-world deployment, and joining at this stage means genuine ownership over that next chapter, working alongside a highly technical team on one of the most consequential problems in AI infrastructure today.
You will be joining a multi-disciplinary research team in the UK, working closely with other engineers, to lead the development of III-V active components – primarily semiconductor optical amplifiers (SOAs) – integrated on our silicon. As the technical owner of our SOA technology, you will take devices from epitaxial stack and device design, through fabrication with our III-V and silicon photonics foundry partners, to characterisation, reliability and qualification.

Requirements

• Ph.D. in physics, photonics, electrical engineering, optical engineering or a related subject with 6+ years’ relevant experience, or a Master’s degree with 8+ years’ relevant experience; including at least 4 years’ hands-on development of III-V SOAs or semiconductor lasers, preferably in industry
• Demonstrated track record of taking SOAs (or semiconductor lasers) from concept through design, fabrication and test, ideally including devices taken through qualification
• Deep understanding of semiconductor laser and amplifier physics: optical gain, carrier dynamics, quantum-well design, amplified spontaneous emission and noise, gain saturation and nonlinearities, thermal effects and polarisation dependence
• Hands-on knowledge of III-V epitaxy and fabrication processes (e.g. MOCVD/MBE growth, lithography, etching, passivation, metallisation, facet/AR coating), and experience working with external foundries
• Experience with characterising SOAs or lasers, including optical spectrum analysers, gain and noise-figure measurement, wafer-level probing, temperature-controlled testing and test automation
• Experience with mainstream simulation and layout tools for active and passive photonic devices, such as Lumerical (including MQW/CHARGE/HEAT), Photon Design (PICWave, FIMMWAVE/Harold), Crosslight, RSoft, COMSOL, KLayout, L-Edit or Cadence Virtuoso
• Proven ability to lead technical projects and coordinate across design, process, test and packaging functions, together with experience mentoring or supervising engineers
• Excellent communication skills, critical thinking, attention to detail and self-motivation

Nice To Haves

• Experience integrating III-V active devices with silicon photonics, including mode conversion and coupling design between III-V and silicon waveguides
• Experience line-managing a technical team, including recruitment and performance development
• Experience with reliability testing and failure analysis of III-V devices (e.g. accelerated ageing, catastrophic optical damage)
• Experience developing PDK building blocks or compact models for active devices
• Experience in programming languages, such as Python, MATLAB or C++, for simulation, test automation and data analysis
• Knowledge of photonic packaging, including fibre coupling, thermal design and TEC control
• Demonstrated ability to generate high quality patents and research papers

Responsibilities

• Work hands-on and lead the design and modelling of III-V SOAs and related active components, including epitaxial layer structure, gain and saturation power modelling, optical mode design, and electrical and thermal design
• Own the SOA technology roadmap and device specifications, translating system requirements (gain, saturation output power, noise figure, polarization dependence, linearity and thermal budget) into device design and integration targets
• Lead mask design and tape-outs: generate and review GDS layouts, test structures and design-of-experiment splits
• Manage fabrication runs with external epitaxy, III-V and silicon photonics foundry partners: define process flows and specifications, review process and in-line data, resolve yield issues and support the transition into volume manufacturing
• Define and lead the characterisation strategy for SOAs at wafer, chip and integrated-PIC level (LIV, gain and ASE spectra, noise figure, saturation output power, polarisation-dependent gain, temperature dependence), including building and automating test setups
• Analyse test data, correlate measured performance with design and process variations, identify performance gaps and drive design iterations to close them
• Work with packaging and reliability engineers on burn-in, accelerated ageing, failure analysis and qualification of SOA devices
• Mentor engineers now and, as the team grows, recruit, line-manage and develop a small team of III-V design and test engineers

What This Job Offers

• Job Type: Full-time
• Career Level: Senior
• Education Level: Ph.D. or professional degree