Lead Embedded CPU PPA Architect

Advanced Micro Devices, Inc•Santa Clara, CA

8d•Hybrid

About The Position

We are seeking a lead PPA Architect to ensure that CPU Core & Cache complexes used in embedded products meets the product performance requirements while operating within reliability and system platform constraints. This is a technical leadership role ensuring interlock between CPU IP definition from the Cores design team and the Embedded BU’s unique per-product usage model and operating conditions, and the package & platform impact to the power delivery network and thermal management.

Requirements

Strong understanding of SoC architecture and design fundamentals: rails, low power modes, performance states, power targets/use cases, platform and system driven constraints.
Working knowledge of PDN and PI principles (IR drop, droop, impedance, decaps, noise budgeting) and ability to drive closure with SIPI/packaging/platform partners.
Working knowledge of device and system reliability requirements, and thermal management algorithms.
Demonstrated ability to lead complex cross‑functional execution (architecture ↔ FW/BIOS ↔ validation ↔ package/platform).
Familiarity collaborating with pre‑silicon power & performance modeling teams and aligning architecture assumptions/targets with projections.
Experience with program milestone readiness (bringing a technical workstream to a “review‑ready” state).
BS/MS in EE/CE (or equivalent) with 7-10 years of relevant experience.

Responsibilities

Align Product Requirements with Cores IP
Drive alignment on usage model (Product Lifetime, % residency in different CPU operating states, etc.), and operating condition constraints (Min/max ambient/case temp, TDC/EDC, customer-specific failure rate specs, etc.) as it impact achievable performance at power.
Drive alignment on power delivery architecture, packaging infrastructure, and platform definition as it impacts assumed power delivery margins and define new margin requirements.
Drive alignment on thermal modeling, packaging & platform definition as it impact assumed thermal operating margins and define new margin requirements.
Translate product usage model, workload, and reliability requirements into IP performance, power, and thermal constraints.
Drive alignment between Embedded BU product roadmap and available CPU IPs, providing critical technical feedback to Embedded product teams and CPU design teams.
Drive alignment and lead technical reviews across the product definition stack: SoC architecture, physical design implementation, package design and platform definition.
Drive power targets and bounding box (BBox) readiness inputs for program reviews, including data-backed tradeoffs (power vs perf vs platform cost/simplicity).
Own a structured “open items” closure mechanism for performance and power topics (risks, dependencies, decisions needed) and represent the workstream in cross‑functional program forums.
Partner closely with the power & performance modeling team to align assumptions, rail targets, use-case definitions, and power feature behaviors that affect model outputs and architectural decisions.
Consume model outputs to drive architecture decisions (budgets, targets, BBox), and provide clear, traceable inputs/constraints back into the modeling loop.
Partner closely with Cores power delivery, thermals, and reliability technical leads to ensure the highly aggressive operating targets are met while simultaneously delivering high performance CPU products.
Provide critical feedback to Embedded BU in these technical areas around SoC, package, and platform design to ensure reliable and robust operation.