Lead Designer, Layout

Analog Devices•Chandler, AZ

1d•Onsite

About The Position

As a Lead Designer, Layout, you will execute full-custom analog and mixed-signal IC layouts from floorplan through signoff, developing parasitic-aware layout strategies that support products spanning multiple ADI business units.

Requirements

7+ years of custom analog/mixed-signal IC layout experience
Strong proficiency with Cadence Virtuoso Layout Suite and physical verification tools (Calibre or Cadence PVS)
Proven track record delivering layouts through tapeout and production release
Proven experience in precision matching layout for bipolar and MOS transistors, resistors, and capacitor arrays in CMOS and BCD processes, including latch-up prevention and substrate isolation to minimize parasitic carrier injection and collection
Proficiency in parasitic extraction, layout-dependent effects, and post-layout simulation correlation
Excellent presentation, technical writing, and communication skills

Nice To Haves

Experience or strong interest in applying AI/ML to layout automation, including generative layout, placement optimization, DRC-aware routing, and predictive parasitic estimation
Proficiency in SKILL scripting or Python/TCL automation for layout productivity
Familiarity with high-voltage and BCD process layout including DMOS/LDMOS metallization for Rdson minimization, gate metal strapping, ESD structures, and multi-voltage domain isolation

Responsibilities

Execute full-custom layout for analog and mixed-signal blocks including power stage FET metallization, LDOs, references, gate drivers, charge pumps, signal conditioning, and data converters (SAR, delta-sigma, pipeline ADC, precision DAC)
Develop block-level and chip-level floorplans optimizing area, routing, power distribution, and signal integrity
Apply precision matching techniques including common centroid, interdigitation, interleaving, merging, and symmetry, with noise isolation through guard rings, shielding, and deep N-well structures
Perform physical verification (DRC, LVS, ERC) and parasitic extraction, collaborating with circuit designers on post-layout optimization and silicon correlation
Support layout methodology improvements and junior designer development through SKILL scripting, AI/ML-driven automation, and knowledge sharing