Lead ASIC Digital Design Engineer
About The Position
We're looking for a skilled Lead ASIC Digital Design Engineer who has meaningful hands-on experience in RTL design and has contributed to complex digital hardware development. This is a technical role for someone who understands the full ASIC/FPGA design lifecycle and is ready to take on real ownership within a collaborative, high-performing team. If your career has been primarily running P&R tools, this probably isn't the right fit. We need an RTL designer at heart — someone who thinks in architecture and microarchitecture, and understands the downstream implications of design decisions. The right candidate is a self-starter who operates with minimal supervision — someone who takes ownership of their work, drives progress independently, and brings solutions rather than waiting to be directed.
Requirements
- 8–12+ years of ASIC/FPGA design experience, with meaningful time spent as an RTL designer
- Experience contributing to ASIC tape-out efforts, including timing closure and physical verification
- Familiarity with FinFET process nodes (7nm, 5nm, or similar) is a meaningful differentiator
- Experience with commercial foundry flows (TSMC, GlobalFoundries, Samsung, or equivalent)
- Working knowledge of: RTL design and microarchitecture, Bus fabric design and verification, Clock domain crossing (CDC) analysis, Reset sequencing and validation, Timing closure at advanced nodes, Power analysis and optimization
- Strong understanding of ASIC/FPGA engineering concepts, RTL coding practices, and synthesis flows
- Familiarity with industry-standard EDA tools (synthesis, simulation, formal verification, STA)
- Ability to operate independently — identifying problems, driving resolution, and keeping work moving without requiring day-to-day direction
- Ability to evaluate vendor and foundry capabilities
- Proficiency in JIRA for issue tracking and backlog management
- Proficiency in Microsoft Office for documentation and communication
Responsibilities
- Own RTL design — Develop and lead RTL with a focus on correctness: bus fabric integrity, clock domain crossings, reset order-of-operations, and design-for-verification
- Drive timing closure — Work through synthesis, place and route, and static timing analysis; understand root causes of timing failures and own fixes through resolution
- Lead verification efforts — Develop and execute test and simulation plans; verify results and drive closure on failures
- Own JIRA triage — Review and prioritize incoming issues; maintain an accurate and actionable backlog
- Lead code reviews — Conduct RTL code reviews, setting technical standards and providing actionable feedback
- Support program planning — Provide input to Integrated Master Schedule (IMS) development and Earned Value (EV) reporting; communicate accurate task status and schedule risk
- Support proposals — Contribute to basis of estimates (BOEs) for proposals, providing accurate technical input on scope, complexity, and level of effort for ASIC/FPGA design tasks
- Evaluate technology — Assess foundry technologies, device libraries, IP cores, and EDA tooling to inform design decisions
- Collaborate broadly — Participate in Integrated Product Teams and working groups across divisions or companies
Benefits
- Highly competitive benefits
- Flexible work environment
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What This Job Offers
Job Type
Full-time
Career Level
Senior
Education Level
No Education Listed
