ASIC Design Engineer Technical Lead
About The Position
The Common Hardware Group (CHG) creates innovative hardware platforms central to the AI era, powering Cisco’s core Switching, Routing, and Wireless products for organizations globally. Our innovations in silicon, optics, and hardware platforms—like Silicon One—are shaping the technology industry. We're a global team of creative experts, bringing our unique backgrounds and bold ideas to push boundaries and help each other grow. Because full product development—from design to qualification to production—is within our team, we’re able to think differently, experiment more, and work quickly. Join us to power the future of the digital world.
Requirements
- Bachelor’s degree in Electrical or Computer engineering and 8+ years of ASIC Design experience, or Master’s degree in Electrical Engineering or Computer Engineering and 6+ years of ASIC Design experience, or PhD in Electrical Engineering or Computer Engineering + 3 years in ASIC Design experience.
- Verilog/System Verilog programming experience.
- Interactive and waveform debug experience.
- Experience delivering ASIC designs from specification to tape-out.
- Experience in architecture and micro architecture development.
Nice To Haves
- Experience resolving setup and hold timing violations with RTL modification.
- Scripting experience (Python, Perl, TCL, shell programming).
- Demonstrated ability in troubleshooting and debugging.
- Good written and verbal communication skills.
Responsibilities
- Participate in and contribute to chip architecture definition and discussions.
- Author design specifications and participate in micro-architecture specification reviews.
- Implement Verilog RTL to meet timing and performance requirements.
- Help define, evolve, and support our design methodology.
- Mentor junior engineers on performing project tasks and problem solving.
- Collaborate with the verification team to address design bugs and close code coverage.
- Work closely with physical design team to close design timing and place-and-route issues.
- Triage, debug, and root cause simulation, software bring-up, and customer failures.
- Perform diagnostic and post silicon validation tests in the lab.
Benefits
- medical, dental and vision insurance
- a 401(k) plan with a Cisco matching contribution
- paid parental leave
- short and long-term disability coverage
- basic life insurance
- grants of Cisco restricted stock units
- 10 paid holidays per full calendar year
- 1 floating holiday for non-exempt employees
- 1 paid day off for employee’s birthday
- paid year-end holiday shutdown
- 4 paid days off for personal wellness
- 16 days of paid vacation time per full calendar year (non-exempt)
- flexible vacation time off program (exempt)
- 80 hours of sick time off provided on hire date and each January 1st thereafter
- up to 80 hours of unused sick time carried forward
- Additional paid time away may be requested to deal with critical or emergency issues for family members
- Optional 10 paid days per full calendar year to volunteer
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What This Job Offers
Job Type
Full-time
Career Level
Senior
