Layout Engineering Manager

OLIX•Austin, TX

6d•Onsite

About The Position

AI is growing faster than any technology in history and the explosion in demand has created a massive infrastructure gap; we can no longer build chips or power stations fast enough to keep up. The industry is still leaning on a ten-year-old hardware blueprint that has reached its limit. A new paradigm that is faster and more efficient will be the biggest economic opportunity of the next century and create the most important company of the next decade. The OLIX Decode Accelerator 1 (DX-1) is the first accelerator architected specifically for decode. Rack-scale co-design of logic, data movement, packaging, optics and interconnect enables a step change in system level performance.

Requirements

8+ years of full-custom analog and mixed-signal IC layout, with at least 3 different taped-out products containing high-speed analog content (multi-GHz bandwidth, multi-GSPS converters, SerDes, or equivalent).
Tape-out experience in advanced CMOS FinFET (16 nm or below); deep familiarity with FinFET-specific design rules, matching, and parasitic implications.
Expert command of the Cadence Virtuoso platform: Layout XL/Suite, Schematic XL, ADE, and constraint-driven / layout-aware flows.
Strong proficiency with at least one industry-standard physical-verification environment (Mentor Calibre or Cadence Pegasus/PVS) for DRC, LVS, antenna, density, and ERC/PERC; able to ramp on the alternate flow.
Hands-on with parasitic extraction and EM/IR-drop tools (Calibre xACT/PEX, Quantus QRC, Voltus, Totem, or equivalent) and post-layout closure methodology.
Working proficiency in SKILL / SKILL++ for layout automation and PCell development; comfort with Python, Tcl, or shell for flow scripting.
Experience managing libraries and design data in a version-controlled / SOS environment (Cadence Team Workflow, Cliosoft SOS, or equivalent).
Solid grounding in semiconductor device physics and the analog implications of layout choices.
Deep working knowledge of analog-layout best practices: device matching (common-centroid, interdigitation, dummy devices), noise isolation (guard rings, deep n-well, substrate-noise separation, supply partitioning), controlled-impedance and differential routing (return-path management, shielding, transmission-line discipline), symmetry, EM/current-density rules, and mitigation of layout-dependent effects (WPE, STI/LOD stress) in advanced nodes.
Demonstrated leadership and people-management skills — scoping work, running layout reviews, mentoring engineers, and managing external contractors — with excellent cross-functional communication in fast-moving, ambiguous environments.

Nice To Haves

Tape-out experience at 7 nm or below, with multi-patterning and color-aware layout.
Advanced PCell development for on-chip passives (custom inductors, transformers, T-coils, baluns) and design-rule-aware automation.
EM simulation of on-chip passives (EMX, Momentum, HFSS, or equivalent) and integration of EM-extracted models into post-layout flows.
Familiarity with coherent optical links, photonic-electronic co-design, or high-bandwidth electro-optic interfaces.
Exposure to AI/ML accelerator silicon, HBM/DDR interfaces, or chiplet / 2.5D / 3D packaging considerations at the layout level.
Contributions to open-source EDA tooling, PCell libraries, or layout-automation frameworks.

Responsibilities

Architect, plan, and execute full-custom analog and mixed-signal layouts — high-speed data converters, SerDes front-ends, PLLs/CDRs, LDOs, bandgaps, TIAs, drivers, and high-bandwidth analog front-ends — in advanced CMOS FinFET nodes.
Own floor-planning, power-grid design, shielding, and signal-integrity strategy for high-speed blocks; partner with circuit designers to meet aggressive PPA, matching, and noise targets.
Lead block- and chip-level AMS integration: hierarchical assembly, abutment planning, ESD/latch-up strategy, antenna mitigation, and seal-ring/PAD-ring construction.
Drive physical-verification, parasitic-extraction, and EM/IR-drop sign-off; iterate with designers on post-layout closure across PVT corners.
Build and own layout automation — SKILL scripts and parameterized Virtuoso PCells (custom inductors, transformers, T-coils, MOM/MIM caps, guard rings, fill structures) — that accelerate the team.
Own the layout PDK/IP library and design-data workflows: device generators, tech files, version-controlled libraries, GDSII/OASIS stream-out, and foundry hand-off.
Plan and execute tape-out: ECO management, metal-only revisions, DFM/DFR sign-off, and cross-functional coordination with package, test, and product-engineering teams.
Lead projects using team comprised of internal and external design-services partners, setting methodology, running design reviews, and unblocking execution.

Benefits

Competitive Salary: $365,000+
Meaningful stock options
$36k annual Living-Local Bonus if your residence is within 20 minutes of the office
33 days of paid time off (PTO), including US federal holidays
Multiple high-quality medical plan options, including family coverage
A high-deductible medical option with a company-funded health savings account (HSA)
Dental and vision coverage
Life insurance, plus short- and long-term disability
Mental health resources, fertility and family-building support
Pre-tax commuter and parking benefits
Access to a 401(k) retirement plan with a 4% employer match, with both traditional and Roth contribution options
Access to a dedicated financial advisor
M4 Macs come as standard, with M4 Pro upgrades for our engineering team
High-spec noise-cancelling headphones and a fully ergonomic workstation
Access to our high-performance 3D printing lab
Chef-prepared meals: if you need to work late
Full UK and international visa sponsorship
Relocation partner provides funding and concierge support