Layout Engineer, DEG

Micron Technology•Boise, ID

About The Position

Micron Technology is seeking a Layout Engineer to perform hands-on physical design work for memory technologies. The role focuses on shaping block-level layouts, guiding physical design strategy, and contributing to the quality and reliability of DRAM products. The engineer collaborates closely with global design, CAD, and verification teams. Responsibilities include creating analog block-level layouts in Cadence Virtuoso, applying physical design methods and constraints, ensuring physical verification and reliability compliance, supporting extraction and post-layout activities, and producing partial custom layouts for selected device-level or small analog blocks.

Requirements

Bachelor's degree in EE, Physics, CE, or a comparable degree.
At least 2 years of hands-on analog layout experience.
Experience performing physical layout using Cadence Virtuoso or similar tools.
Familiarity with DRC, LVS, physical verification, and reliability checks.
Ability to plan, document, and review layout goals with cross-site teams.

Nice To Haves

Good understanding of circuit design principles and ability to develop high-performance layouts optimized for area.
Understanding of how layout affects circuit speed, capacitance, power, and area.
Strong problem-solving skills in physical layout verification.
Scripting and automation experience.
Experience using AI agents to generate layouts.
Strong communication skills supporting global engineering teams.

Responsibilities

Build analog block-level layouts in Cadence Virtuoso, including floorplanning, placement, routing, and optimization.
Apply layout methods and physical constraints such as PDN, pin placement, routing blockages, and hierarchy.
Ensure DRC, LVS, density, and reliability compliance.
Support parasitic extraction, post-layout verification, and ECO activities.
Build partial custom layouts for selected device-level or small analog blocks.