Layout Engineer

Broadcom•Fort Collins, CO

About The Position

This position is part of a highly skilled multi-geographical team tasked with the development of high speed analog, mixed-signal IPs covering HBM, UCIe, PLL, and many others areas using the latest 3nm and 2nm FinFET technology. The team will be developing key differentiating IPs used in the Artificial Intelligence, Machine Learning, High Performance Computing and Hyper-Scale Data Center markets. Each member of the team is expected to be committed to the team success, create new innovation, and ensure customer usage satisfaction with first time right quality mindset.

Requirements

Extensive experience with layout of high-speed custom analog and digital circuits in area(s) like Serdes, HBM, UCIe and PLL.
Extremely familiar with the use of the Cadence Virtuoso tool suite to design and verify high-speed custom circuits, including Virtuoso schematic capture and layout.
Design experience in advanced FinFET nodes is required.
Demonstrated ability to rely on both thorough understanding of layout fundamentals and creativity to solve circuit layout issues and problems.

Nice To Haves

Innovus a plus.

Responsibilities

Layout and verification of circuits to be used as part of state-of-the-art integrated circuits including: PLLs, Phase Interpolators High speed clock distribution networks Rx Decision-Feedback Equalizers and deserializers TX drivers and serializers High Speed DACs and ADCs
Developing detailed layout and performing all necessary verifications.
Optimizing layout of circuits for power, performance, and integration to higher level IP / SOCs.