Intern Engineer - Digital IC Design (AI-Assisted Design Focus)
About The Position
Huawei Canada has an immediate 6-8 month internship opening for an Engineer. About the team: Initially founded in 1991 as Huawei's ASIC Design Center, the IC Lab is a leading global fabless semiconductor lab. This lab delivers trusted, cutting-edge semiconductor products and services for smart devices, contributing to smart home and mobility solutions. The local team in Canada specializes in semiconductors, and chipset solutions. About the job: Participate in digital IC module design, including: o RTL design using Verilog/SystemVerilog o Module-level implementation and optimization Assist in key stages of the design flow, including: o Simulation and functional verification o Synthesis and Static Timing Analysis (STA) o Power, Performance, and Area (PPA) optimization Contribute to AI-assisted EDA exploration, including but not limited to: o Applying machine learning techniques to optimize synthesis and placement & routing o Automated RTL generation and optimization (e.g., LLM-based or rule-based approaches) o Design Space Exploration (DSE) Develop scripts to improve design automation (Python, TCL, etc.) Collaborate with architecture, verification, and physical design teams to support project delivery The total target annual compensation for this position ranges from $58,000 to $104,000 depending on education, experience, and demonstrated expertise.
Requirements
- Currently pursuing a Master’s degree or PhD in Electrical Engineering, Computer Engineering, Microelectronics, Integrated Circuits, or a related field
- Solid understanding of digital design fundamentals:
- Sequential and combinational logic
- Finite State Machine (FSM) design
- Synchronous design principles (e.g., CDC, clock domains)
- Proficiency in at least one hardware description language: Verilog or SystemVerilog
- Familiarity with Linux environments and basic scripting skills (Python, Shell, or TCL), familiarity with mainstream EDA tools (e.g., Synopsys or Cadence tool flows)
- Experience in at least one of the following:
- RTL design projects (coursework, internships, or open-source projects)
- FPGA development
Nice To Haves
- Experience with AI-assisted EDA is an asset:
- Applying machine learning to EDA optimization (e.g., timing prediction, congestion prediction)
- Familiarity with AI4EDA-related research or projects (e.g., work from Google Brain / DeepMind)
- Experience in one or more of the following areas is an asset:
- Design flow automation
- RTL/code generation tools (e.g., LLM-based approaches)
- Reinforcement learning applications in chip design
- Knowledge in at least one of the following domains is an asset:
- High-speed interfaces (SerDes)
- AI accelerators (NPU/GPU)
- SoC architecture design
Responsibilities
- Participate in digital IC module design
- RTL design using Verilog/SystemVerilog
- Module-level implementation and optimization
- Simulation and functional verification
- Synthesis and Static Timing Analysis (STA)
- Power, Performance, and Area (PPA) optimization
- Contribute to AI-assisted EDA exploration
- Applying machine learning techniques to optimize synthesis and placement & routing
- Automated RTL generation and optimization (e.g., LLM-based or rule-based approaches)
- Design Space Exploration (DSE)
- Develop scripts to improve design automation (Python, TCL, etc.)
- Collaborate with architecture, verification, and physical design teams to support project delivery
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What This Job Offers
Career Level
Intern
Number of Employees
5,001-10,000 employees
