Intern - DRAM Design Rules

Micron Technology • Boise, ID

3d

About The Position

The DRAM Design Rules team develops and maintains design rules, methodologies, and automation solutions that enable the successful design and manufacturing of advanced memory technologies. The team partners closely with Design, CAD, Process Integration, Verification, and Product Engineering organizations to ensure technology scalability, design quality, and manufacturing robustness. As a DRAM Design Rules Intern, you will contribute to design rule development, validation, automation, and design enablement activities for next-generation memory products. This role provides hands-on experience with semiconductor build methodologies, industry-standard EDA tools, AI Supported analytics, and multi-functional engineering collaboration while helping drive future memory technology innovation.

Requirements

• Currently pursuing a Bachelor's, Master's, or PhD degree in Electrical Engineering, Computer Engineering, Semiconductor Engineering, Physics, Computer Science, or a related engineering discipline.
• Fundamental understanding of semiconductor devices, CMOS circuits, and semiconductor manufacturing processes.
• Programming or scripting experience using Python, Tcl, Perl, or similar languages.
• Demonstrated analytical, problem-solving, and debugging skills.
• Effective written and verbal communication skills with the ability to collaborate within multi-functional engineering teams.

Nice To Haves

• Coursework, research, or project experience in VLSI Design, Physical Design, Layout Design, Design Rule Checking (DRC), Physical Verification, or semiconductor device physics and processing.
• Experience using EDA tools such as Cadence Virtuoso, Calibre, Synopsys, or equivalent semiconductor design and verification platforms.
• Experience with physical verification activities including DRC, LVS, parasitic extraction, layout debugging, or semiconductor validation methodologies.
• Experience developing Python-based automation, software development, workflow optimization solutions, or design enablement tools.
• Familiarity with data analytics, machine learning, Artificial Intelligence, Generative AI, Large Language Models (LLMs), AI Agents, Agentic AI, Cloud Assist, Code Assist, Roo Code, or other AI-Enabled engineering applications used to support technical analysis, automation, and productivity improvements.
• Exposure through coursework, research, or internship experience to semiconductor test chip design, silicon characterization, validation, process monitoring, advanced CMOS technologies, DRAM, HBM, or semiconductor automation.

Responsibilities

• Assist in the development, documentation, validation, and optimization of semiconductor design rules for advanced memory technologies.
• Support design enablement activities by developing methodologies, automation solutions, scripts, and workflows that improve design productivity, verification quality, and engineering efficiency.
• Perform design rule validation, verification, and analysis using industry-standard EDA tools, simulation environments, and AI Supported analytics frameworks.
• Collaborate with Design, CAD, Process Integration, Verification, and Product Engineering teams to evaluate technology features, process changes, and manufacturability requirements.
• Support test chip planning, validation activities, and data analysis by using AI. Apply Artificial Intelligence technologies to speed up learning cycles and improve development methods.

Benefits

• Choice of medical, dental and vision plans
• Benefit programs that help protect your income if you are unable to work due to illness or injury
• Paid family leave
• Robust paid time-off program
• Paid holidays

What This Job Offers

• Job Type: Full-time
• Career Level: Intern
• Education Level: No Education Listed