Ayar Labs is seeking a motivated graduate or Ph.D. intern to join its CTO architecture team, which analyzes electro-optical boundaries, signal integrity, and performance limits of next-generation interconnects. The intern will work on electrical integrated circuit/photonic integrated circuit (EIC/PIC) co-optimization and model architecture performance. The work will include evaluating near-packaged optics (NPO) and co-packaged optics (CPO) paradigms in alignment with emerging OCI MSA specifications, in collaboration with mixed-signal designers, photonics engineers, and system architects. The project will be tailored to the intern’s background, with mentorship from a senior link architect. The internship term is May to August 2027. The position is on-site at the San Jose office. Immigration support is not available except for F-1 status, and relocation support is not offered. The posting expires upon reaching its application threshold.
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Career Level
Intern
Education Level
Ph.D. or professional degree