Ayar Labs is seeking a motivated graduate or Ph.D. intern to join its CTO architecture team. The team analyzes electro-optical boundaries, signal integrity, and the performance limits of next-generation interconnects to advance optical I/O. The intern will work on electrical integrated circuit/photonic integrated circuit (EIC/PIC) co-optimization and architecture performance modeling, collaborating with mixed-signal designers, photonics engineers, and system architects to evaluate near-packaged optics (NPO) and co-packaged optics (CPO) paradigms in alignment with emerging OCI MSA specifications. The project will be tailored to the intern’s background, with mentorship from a senior link architect. The position is an on-site internship in Ayar Labs’ San Jose office, running from May through August 2027. Immigration support is not provided except for F-1 candidates, and relocation support is not provided.
Stand Out From the Crowd
Upload your resume and get instant feedback on how well it matches this job.
Career Level
Intern
Education Level
Ph.D. or professional degree