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Astera Labs • San Jose, CA

1d

About The Position

Astera Labs is seeking a highly motivated and team-oriented Integrated Circuit Designer - Layout to join a key team designing and developing sophisticated advanced node CMOS products. This role involves collaborating with both layout and design engineers across multiple time zones. The designer will be responsible for the design and development of integrated circuit layouts according to electronics engineering principles, using software to create design schematics and diagrams. This includes floor planning, creating layouts of building blocks, and integrating layouts for circuits such as PLL, DLL, ADC, regulators, amplifiers, TX, RX, and CDRs in advanced CMOS nodes. A key focus will be on minimizing parasitic and skew, matching, EMIR, and antenna rules, in addition to DRC and LVS.

Requirements

• At least a bachelor’s degree in electrical engineering
• 10+ years of experience in the development of layouts for highspeed analog IC designs in fin FET technology.
• Experience with layout extraction tools and to analyzing layout parasitic to achieve high quality layout for highspeed circuits.
• EMIR and antenna DRC rules aware layout practices.

Nice To Haves

• Experience writing SKILL and TCL scripts is highly recommended

Responsibilities

• Design and development of the layout for integrated circuits according to electronics engineering principles, using software to create design schematics and diagrams.
• Floor planning, creating layouts of building blocks and integrating layouts for circuits such as PLL, DLL, ADC, regulators, amplifiers, TX, RX, and CDRs in advanced CMOS nodes.
• Minimizing parasitic and skew, matching, EMIR, and antenna rules on top of DRC and LVS.
• Management of manufacturing process of the products, including technology yield and performance of the products.
• Development of test programmes and procedures to ensure the products meet their performance specifications.
• Provision of advice on aspects of semiconductor process technology and maintain and repair semiconductor process equipment.

Benefits

• Competitive salary
• 13th month salary
• Performance bonus each year
• Long Term Incentive (LTI)
• Health check each year
• Insurance for engineer and family
• Lunch Allowance
• Company trips

What This Job Offers

• Job Type: Full-time
• Career Level: Senior