IC Verification Engineer

Broadcom•San Jose, CA

1d•$143,800 - $230,000

About The Position

The IC Verification Engineer will be responsible for architecting and developing scalable and reusable Testbench environments using Verification Methodologies. This role involves driving test plans for all features at the Block/Core/SOC level, writing functional coverage, and building pseudo-random tests to achieve full functional coverage and bring verification to closure. The engineer will also debug regression failures, analyze functional coverage gaps, and improve tests accordingly. Collaboration with team members, mentoring junior engineers, and thinking innovatively to stress and verify the DUT efficiently are key aspects of this position. The role also includes leading the documentation of verification strategy, including test plans and verification environments, and leading reviews with design/architecture teams. Driving verification quality and efficiency improvements is also a core responsibility.

Requirements

Bachelor's degree in Electrical/Electronics/Equivalent with 12+ years of experience; or Masters degree in Electrical/Electronics/Equivalent with 10+ years of experience
10+ years of experience in developing complex Verification Environments, developing Test plans, Functional coverage and pseudo-random testing
Must have gone through a full ASIC cycle right from Architecture development to Tapeout with full focus on Verification
Very proficient in System Verilog and Verification Methodologies like UVM/VMM
Good debug skills in analyzing regression failures and understanding of complex designs
A good understanding of a complex protocol like PCI Express or other multi-layered protocol
Work with the team and mentor junior engineers

Nice To Haves

Experience in PCIe protocol
Scripting knowledge of Python or Perl
Comfort with Makefiles
Experience with Verifying with other protocols like AXI

Responsibilities

Architect and develop scalable and reusable Testbench environment using the framework of Verification Methodologies.
Drive Test plans for all features for Block/Core/SOC and Write Functional coverage for these features.
Build pseudo-random tests to verify and get to full Functional coverage and bring the Verification to closure
Debug Regression failures, analyze Functional Coverage gaps and improve tests to cover the gaps
Work with other members of the team, guide/mentor junior team members
Think differently and out-of-the-box to stress the DUT and verify it in an efficient way.
Lead the documentation of verification strategy including Test plans, Verification Environment, pseudo-random tests, etc. Lead reviews with design/architecture.
Driver Verification quality and Efficiency improvements