IC Design Engineer

Broadcom • San Jose, CA

1d • $143,800 - $230,000

About The Position

This role is for an IC Design Engineer with a focus on Design for Testability (DFT). The engineer will be responsible for top-level DFT planning and integration, managing ATPG and ATE interfaces, and optimizing test time. The position also involves synthesis, formal verification, STA, simulation for DFT modes, and implementing DFT across multi-power domain designs. Troubleshooting DFT-related issues and improving DFT flows are also key responsibilities.

Requirements

• Extensive experience with the Siemens Tessent tool suite.
• Bachelors and 12+ years of related experience, or Masters degree and 10+ years of related experience.
• Experience with ATPG and ATE interface management.
• Experience with synthesis, formal verification, STA, and simulation for DFT modes.
• Experience with DFT across multi-power domain designs.

Nice To Haves

• Post-graduate degree is typically expected at this level.

Responsibilities

• Top-level DFT planning and integration.
• Managing ATPG (Automatic Test Pattern Generation) and ATE (Automated Test Equipment) interface, including ATE bring-up and failure analysis.
• Driving test time reduction strategies.
• Handling synthesis, formal verification, and performing STA (Static Timing Analysis) & Simulation specifically for DFT modes.
• Implementing DFT across multi-power domain designs.
• Troubleshooting DFT-related issues and continuously driving DFT flow improvements.

Benefits

• Discretionary annual bonus
• Competitive new hire equity grant
• Annual equity awards
• Medical plans
• Dental plans
• Vision plans
• 401(K) participation
• Company matching for 401(K)
• Employee Stock Purchase Program (ESPP)
• Employee Assistance Program (EAP)
• Company paid holidays
• Paid sick leave
• Vacation time
• Paid Family Leave
• Other leaves of absence

What This Job Offers

• Job Type: Full-time
• Career Level: Senior