IC Design Engineer

Broadcom • San Jose, CA

1d • $143,800 - $230,000

About The Position

We are a global technology leader that designs, develops and supplies a broad range of semiconductor and infrastructure software solutions. For more information please visit our video library and check out our Connected by Broadcom series. Follow us on Linked In Broadcom Inc.

Requirements

• Extensive experience with the Siemens Tessent tool suite.
• Bachelors and 12+ years of related experience; at this level a post-graduate degree is typically expected or Masters degree and 10+ years of related experience.

Responsibilities

• Responsible for top-level DFT planning and integration.
• Managing the ATPG (Automatic Test Pattern Generation) and ATE (Automated Test Equipment) interface, including ATE bring-up and failure analysis.
• Driving test time reduction strategies.
• Handling synthesis, formal verification, and performing STA (Static Timing Analysis) & Simulation specifically for DFT modes.
• Implementing DFT across multi-power domain designs.
• Troubleshooting DFT-related issues and continuously driving DFT flow improvements.

Benefits

• Discretionary annual bonus
• Competitive new hire equity grant
• Annual equity awards
• Medical, dental and vision plans
• 401(K) participation including company matching
• Employee Stock Purchase Program (ESPP)
• Employee Assistance Program (EAP)
• Company paid holidays
• Paid sick leave
• Vacation time
• Paid Family Leave
• Other leaves of absence

What This Job Offers

• Job Type: Full-time
• Career Level: Senior