High-Speed Interface Validation Engineer, Post Silicon Validation

Amazon • Austin, TX

1d • $143,700 - $194,400 • Onsite

About The Position

Join our Post-Silicon Validation team to validate the critical high-speed interconnects — HBM, PCIe, UCIe, and chip-to-chip links — that enable massive bandwidth and scaling in AWS's next-generation ML accelerators. You'll ensure link integrity, performance, and reliability at the electrical and protocol layers across the full product lifecycle, from first silicon through production deployment in AWS data centers. You'll work in a fast-paced, startup-like environment alongside some of the brightest minds in the industry on next generation, internet-scale technology that directly impacts how customers use Machine Learning acceleration. Your expertise will be instrumental in validating the I/O technologies that enable our custom silicon to scale beyond what was previously possible.

Requirements

• 3+ years of non-internship professional software development experience
• 2+ years of non-internship design or architecture (design patterns, reliability and scaling) of new and existing systems experience
• Experience with RF measurement equipment, including: power meters, spectrum analyzers, vector signal generators, network analyzers, oscilloscopes
• Bachelor's degree in Computer Science, Computer Engineering, or Electrical Engineering, or experience in test setup automation using MATLAB, Python, or Pearl
• 3+ years of hands-on experience validating or characterizing at least one high-speed interface technology (HBM, PCIe, DDR, SerDes, or UCIe)
• Proficiency with signal integrity measurement techniques: eye diagram analysis, jitter decomposition, and voltage/timing margin assessment
• Familiarity with at least one interface specification standard (JEDEC HBM/DDR, PCI-SIG PCIe, or UCIe consortium)

Nice To Haves

• 3+ years of full software development life cycle, including coding standards, code reviews, source control management, build processes, testing, and operations experience
• Experience with HBM PHY training sequences and characterization
• Knowledge of forward error correction (FEC) and link reliability metrics (BER, MTBF)
• PCB and package-level signal integrity awareness (S-parameters, channel modeling)
• Experience with multi-die or chiplet architectures and die-to-die interconnect validation
• Familiarity with equalization techniques (CTLE, DFE, FFE) and adaptive tuning

Responsibilities

• Validate high-speed interfaces (HBM, PCIe, UCIe, custom SerDes) end-to-end from PHY training through sustained traffic
• Perform electrical characterization: eye diagrams, jitter analysis, voltage margin, and equalization tuning
• Execute protocol-level compliance testing and interoperability validation against industry specifications
• Stress-test links across PVT (Process, Voltage, Temperature) corners and aging conditions
• Debug link training failures, bit errors, and performance degradation using lab instrumentation and silicon debug features
• Collaborate with PHY design teams on equalization optimization, margin improvement, and silicon feedback

Benefits

• sign-on payments
• restricted stock units (RSUs)
• health insurance (medical, dental, vision, prescription, Basic Life & AD&D insurance and option for Supplemental life plans, EAP, Mental Health Support, Medical Advice Line, Flexible Spending Accounts, Adoption and Surrogacy Reimbursement coverage)
• 401(k) matching
• paid time off
• parental leave

What This Job Offers

• Job Type: Full-time
• Career Level: Mid Level