Head of Memory Architecture (Xora Portfolio Company)

Xora Innovation•San Jose, CA
•Onsite

About The Position

We are a Silicon Valley, San Jose based stealth start-up looking for a passionate, ambitious individual who shares our vision of next generation disruptive memory solutions for Agentic AI inference and high performance data center computing applications. This is an impactful and senior leadership role allowing you to mastermind the realization of our strategic ambitions and shape the direction of our product portfolio development.

Requirements

  • M.S. or Ph.D. in Computer Science (CS), Computer Engineering (CE), or Electrical Engineering (EE) preferred.
  • 10+ years in memory architecture, preferably the leading memory IDMs.
  • Deep grasp of state-of-the-art memory issues and challenges particularly associated with Agentic AI inference computing.
  • Power, performance, area and cost (PPAC) analysis and modeling.
  • Broad network of relevant industry and academia experts to deepen our understanding and to evangelize our memory offering.

Responsibilities

  • Lead the architectural design of our disruptive product which is a purpose-built memory for AI inference computing, building on your extensive knowledge and industry experience combined with our proprietary in-house device technology capabilities.
  • Design, model, and optimize the memory subsystems for a new memory category and product for AI inference computing.
  • Balance memory footprint, bandwidth, latency, power efficiency, density, silicon area, and cost/bit.
  • Design memory vaults and hierarchies, on-chip interconnects, sense amplifiers and address translation with emphasis on high granularity and bandwidth.
  • Analyze state-of-the-art Agentic AI inference applications, software, AI inference models, leading edge SOCs for data center workloads and how they interact with memory to reduce bottlenecks.
  • Benchmark leading edge AI inference SOC architectures and workload management specifics vis a vis competing memory architectures and devices including our disruptive memory solution.
  • Understand and leverage our core materials and device technology to realize a category defining memory for inference computing.
  • Partner with SOC architects, NPI teams, silicon design and technology teams to drive acceleration of the product to market.
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