HBM PHY System Architect (San Diego, US)
Qualcomm•San Diego, CA
•$164,000 - $246,000•Onsite
About The Position
QCT mixed-signal IP design team is looking for skilled system architects to design high-speed, high-performance, and low-power HBM Phys. You’ll help with system definition, architecture, and end-end design cycle - starting from early ideas all the way to final chip production and validation.
Requirements
- 5+ years of experience in HBM PHY architecture and design for high-performance memory interfaces.
- Strong understanding of JEDEC memory standards (HBM, LPDDR, DDR) and their application to PHY architecture and design.
- Expertise in link budgeting, timing closure, margin analysis, and PHY training methodologies for high-speed interfaces.
- Proven ability to drive technical discussions and collaborate effectively across cross-functional and globally distributed teams.
- Bachelor's degree in Science, Engineering, or related field and 6+ years of ASIC design, verification, validation, integration, or related work experience.
- Master's degree in Science, Engineering, or related field and 5+ years of ASIC design, verification, validation, integration, or related work experience.
- PhD in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience.
Nice To Haves
- Familiarity with signal integrity (SI), power integrity (PI), package effects, and power delivery networks for high-speed memory systems.
- Knowledge of advanced process technologies, mixed-signal design principles, and high-speed interface implementation.
- Understanding of design-for-yield, manufacturability, and production challenges associated with high-speed memory links.
- Proficiency in Unix/Linux environments and scripting languages such as Perl, TCL, or Python for automation and analysis.
Responsibilities
- Own the HBM PHY architecture and system definition, driving end-to-end solutions that meet performance, power, area, and reliability targets.
- Develop and manage system timing budgets across on-die, and off-chip interfaces, ensuring robust operation across all conditions.
- Lead cross-functional architectural trade-offs and execution, working closely with SoC, memory, package, and validation teams.
- Deliver best-in-class HBM PHY solutions through technical leadership, innovation, and alignment with product roadmap requirements.
Benefits
- competitive annual discretionary bonus program
- opportunity for annual RSU grants
- highly competitive benefits package
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What This Job Offers
Job Type
Full-time
Career Level
Senior
