Hardware & Silicon Validation Senior Staff Engineer

Marvell Technology•Santa Clara, CA

About The Position

About Marvell Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact The Custom Cloud Solutions (CCS) Hardware Validation Group is responsible for ensuring the quality, reliability, and performance of next generation data center ASIC and SoC products spanning a diverse portfolio that includes cloud infrastructure, AI accelerators, network processors, NICs, custom ASICs, SSD controllers, CXL devices, and domain specific accelerators. The team owns end to end hardware validation, working across the product lifecycle from early silicon bring up through system level qualification. Our scope includes functional hardware validation, electrical characterization, high speed SERDES validation, and system/platform validation, all executed in advanced, fully instrumented hardware labs. The group validates complex, high-performance silicon and platforms across a wide range of critical technologies and interfaces, including Memory Subsystems (DDR, HBM, memory controllers), High Speed Interconnects (PCIe, Ethernet, CPRI, PAM4/NRZ), D2D interconnects, Storage, and IO (Flash and NVME, SSD controllers, USB) and System and Platform testing.

Requirements

Bachelor’s degree in Computer Science, Electrical Engineering, or a related field with 5–15 years of relevant industry experience; or Master’s degree and/or PhD in Computer Science, Electrical Engineering, or a related discipline with 3–10 years of professional experience.
Deep expertise in Ethernet Physical Layer technologies (Layer 1 and Layer 2), including SerDes, PCS, and MAC, with hands‑on experience debugging L1 interoperability issues across systems and vendors.
Hands‑on experience with networking and lab test equipment, such as traffic generators (Ixia, Spirent, Xena), protocol analyzers, oscilloscopes, and logic analyzers.
Excellent debugging and troubleshooting skills, with the ability to isolate and resolve complex silicon, system‑level, and interoperability issues, and provide technical support to both internal teams and external customers.
Extensive experience interpreting, contributing to, and implementing networking communication standards from organizations such as IEEE, IETF, or similar standards bodies.
Strong programming expertise in C or equivalent low‑level networking languages, with experience developing, debugging, or optimizing networking software or firmware.

Nice To Haves

Strong familiarity with high‑speed Ethernet SerDes technologies, including NRZ and PAM‑4 signaling, with experience supporting 100G and higher data rates considered a strong plus.

Responsibilities

Lead post‑silicon validation, characterization, and debug of high‑speed Ethernet and PHY interface IPs, ensuring compliance with performance, reliability, and interoperability requirements.
Perform comprehensive Ethernet protocol compliance and standards validation in accordance with IEEE 802.3 and IEEE 802.1Q, including Layer 2 and Layer 3 feature validation such as VLAN, ARP, STP, DHCP, DNS, TCP/IP, OSPF, and BGP.
Execute Ethernet interoperability testing, including link training, auto‑negotiation, and compatibility validation with a wide range of switches, SFP/QSFP modules, DACs, and optical transceivers.
Design, develop, and maintain Python‑based automation frameworks to support functional, regression, and manufacturing tests, significantly improving validation efficiency and reducing manual effort.
Configure, maintain, and scale lab environments to support software validation, networking feature testing, and system‑level stress testing.
Integrate automated test execution into CI/CD pipelines using tools such as Jenkins, analyze test failures, and perform detailed root‑cause analysis to drive corrective actions.
Develop and maintain bare‑metal embedded test software in C/C++ to control, configure, and validate high‑speed network processor ASIC SoCs across multiple product lines.
Collaborate closely with silicon design, validation, firmware/software, and systems teams to ensure hardware and system designs meet stringent performance, reliability, and compliance standards.
Provide customer support and escalation handling, including reproducing field issues in‑house, debugging complex system‑level problems, validating fixes, and supporting customer deployments.