Hardware & Silicon Validation Senior Staff Engineer

Marvell Technology•Santa Clara, CA

About The Position

About Marvell Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact The Custom Cloud Solutions (CCS) Hardware Validation Group is responsible for ensuring the quality, reliability, and performance of next generation data center ASIC and SoC products spanning a diverse portfolio that includes cloud infrastructure, AI accelerators, network processors, NICs, custom ASICs, SSD controllers, CXL devices, and domain specific accelerators. The team owns end to end hardware validation, working across the product lifecycle from early silicon bring up through system level qualification. Our scope includes functional hardware validation, electrical characterization, high speed SERDES validation, and system/platform validation, all executed in advanced, fully instrumented hardware labs. The group validates complex, high performance silicon and platforms across a wide range of critical technologies and interfaces, including Memory Subsystems (DDR, HBM, memory controllers), High Speed Interconnects (PCIe, Ethernet, CPRI, PAM4/NRZ), D2D interconnects, Storage, and IO (Flash and NVME, SSD controllers, USB) and System and Platform testing.

Requirements

Bachelor’s degree in Computer Science, Electrical Engineering, or a related field with 5–15 years of relevant industry experience; or Master’s degree and/or PhD in Computer Science, Electrical Engineering, or a related discipline with 3–10 years of professional experience.
Strong understanding of PCIe and CXL protocol, architecture, and electrical standards, including clocking architectures, reset schemes, power management, speed change mechanisms, and equalization techniques.
Extensive knowledge of physical and protocol layers—including PIPE interface, PCS, and MAC—for one or more common high‑speed interfaces.
Proven experience in system bring-up, validation, and debug, with strong root-cause analysis capabilities.
Experience developing firmware in C to support system bring-up, validation, and debug activities.
Proficient in using PCIe exercisers, analyzers, and jammers for validation and debugging.
Comfortable working with standard lab equipment, including logic analyzers and oscilloscopes.
Experience writing automation scripts (Python or similar languages) for silicon testing and lab automation.
Strong communication skills in English, both written and verbal.
Demonstrated ability to be flexible, proactive, and collaborative, with a strong aptitude for working effectively in a team environment.

Nice To Haves

Hands-on experience with PCIe Gen6 and PAM4 SERDES is highly desirable.

Responsibilities

Lead system bring‑up, validation, and debug activities for platforms utilizing PCIe, CXL and other high‑speed interfaces.
Analyze and resolve complex hardware, firmware, and protocol‑level issues, performing detailed root‑cause analysis and proposing effective corrective actions.
Develop and maintain firmware (C programming) to support system initialization, feature enablement, validation, and debug.
Work extensively with PCIe and CXL protocol architecture and electrical standards, including clocking, reset sequencing, power management, equalization, and speed changes.
Support and debug physical and protocol layers (PIPE interface, PCS, MAC) of PCIe and other high‑speed interfaces.
Utilize PCIe exercisers, analyzers, and jammers to validate functionality, performance, and compliance.
Operate standard lab equipment, including logic analyzers and oscilloscopes, to perform signal integrity analysis and system debugging.
Write and maintain automation scripts (Python or similar) to streamline silicon testing, validation flows, and lab automation.
Collaborate closely with architecture, design, firmware, validation, and product engineering teams to ensure seamless integration and issue resolution.
Document findings, test results, and debug methodologies, and communicate clearly with internal stakeholders.
Contribute to continuous improvement of validation methodologies, debug processes, and lab infrastructure.
Demonstrate flexibility and initiative to take ownership of technical challenges in a dynamic development environment.