Hardware & Silicon Validation Senior Staff Engineer

Marvell Technology•Santa Clara, CA

About The Position

About Marvell Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact The Custom Cloud Solutions (CCS) Hardware Validation Group is responsible for ensuring the quality, reliability, and performance of next generation data center ASIC and SoC products spanning a diverse portfolio that includes cloud infrastructure, AI accelerators, network processors, NICs, custom ASICs, SSD controllers, CXL devices, and domain specific accelerators. The team owns end to end hardware validation, working across the product lifecycle from early silicon bring up through system level qualification. Our scope includes functional hardware validation, electrical characterization, high speed SERDES validation, and system/platform validation, all executed in advanced, fully instrumented hardware labs. The group validates complex, high-performance silicon and platforms across a wide range of critical technologies and interfaces, including Memory Subsystems (DDR, HBM, memory controllers), High Speed Interconnects (PCIe, Ethernet, CPRI, PAM4/NRZ), D2D interconnects, Storage, and IO (Flash and NVME, SSD controllers, USB) and System and Platform testing. What You Can Expect • Lead electrical characterization, compliance, and debug for SerDes IP targeting Ethernet IEEE 802.3ck/dj and PCIe Gen5/Gen6 standards at 112G/224G data rates. • Develop and implement automated validation methodologies, regression frameworks, and compliance test plans for SerDes interfaces across multiple product lines. • Drive signal integrity analysis and optimization for high-speed channels, including correlation between pre-silicon modeling, simulation, and lab measurements. • Own the end-to-end SerDes validation strategy for assigned product programs, from test plan development through production readiness sign-off. • Provide technical leadership and applications engineering support to strategic customers, including on-site debug and performance optimization. • Define and manage equipment CAPEX plans for advanced test equipment; ensure measurement infrastructure readiness for current and next-generation SerDes IP. • Mentor and develop staff-level and junior engineers in high-speed signal integrity measurement techniques, debug methodologies, and test automation best practices. • Collaborate closely with SerDes design, architecture, and product engineering teams to drive silicon quality from early bring-up through volume production. • Contribute to high-speed board design reviews, extraction, and characterization; partner with internal tools teams to build robust test infrastructure. • Author technical collateral including validation reports, application notes, and best-known-methods documentation for internal and customer use. • Represent Marvell in industry forums and customer technical reviews; contribute to standards awareness for IEEE 802.3 and PCI-SIG specifications.

Requirements

Bachelor’s degree in Computer Science, Electrical Engineering, or a related field with 3–15 years of relevant industry experience; or Master’s degree and/or PhD in Computer Science, Electrical Engineering, or a related discipline with 2–10 years of professional experience.
5–7+ years of direct experience in SerDes characterization, design, or signal integrity engineering.
Deep expertise in Ethernet IEEE 802.3ck/dj electrical compliance and validation, and/or PCIe Gen5/Gen6 specifications.
Strong knowledge of signal integrity principles, channel modeling, S-parameter analysis, equalization architectures (CTLE, DFE, FFE), and board-level design for high-speed interfaces.
In-depth working knowledge of test equipment used for SerDes characterization: real-time and sampling oscilloscopes, BERTs, vector network analyzers, pattern generators, and protocol analyzers.
Strong proficiency in Python scripting for test automation, data analysis, and regression infrastructure development.
Demonstrated ability to lead technical projects and mentor engineers.
Experience correlating pre-silicon simulations with post-silicon measurements and driving closure on discrepancies.

Nice To Haves

Experience with high-speed PCB design, signal integrity simulation tools (HFSS, ADS, Sigrity, or equivalent), and channel extraction methodologies is preferred
Active participation or familiarity with IEEE 802.3 or PCI-SIG standards committees is preferred.
Critical thinking and problem-solving attitude with ownership of the group’s results.
Excellent verbal and written communication skills; ability to present technical content to customers and executive leadership.

Responsibilities

Lead electrical characterization, compliance, and debug for SerDes IP targeting Ethernet IEEE 802.3ck/dj and PCIe Gen5/Gen6 standards at 112G/224G data rates.
Develop and implement automated validation methodologies, regression frameworks, and compliance test plans for SerDes interfaces across multiple product lines.
Drive signal integrity analysis and optimization for high-speed channels, including correlation between pre-silicon modeling, simulation, and lab measurements.
Own the end-to-end SerDes validation strategy for assigned product programs, from test plan development through production readiness sign-off.
Provide technical leadership and applications engineering support to strategic customers, including on-site debug and performance optimization.
Define and manage equipment CAPEX plans for advanced test equipment; ensure measurement infrastructure readiness for current and next-generation SerDes IP.
Mentor and develop staff-level and junior engineers in high-speed signal integrity measurement techniques, debug methodologies, and test automation best practices.
Collaborate closely with SerDes design, architecture, and product engineering teams to drive silicon quality from early bring-up through volume production.
Contribute to high-speed board design reviews, extraction, and characterization; partner with internal tools teams to build robust test infrastructure.
Author technical collateral including validation reports, application notes, and best-known-methods documentation for internal and customer use.
Represent Marvell in industry forums and customer technical reviews; contribute to standards awareness for IEEE 802.3 and PCI-SIG specifications.