Hardware & Silicon Validation Principal Engineer

Marvell Technology•Santa Clara, CA

About The Position

About Marvell Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact The Custom Cloud Solutions (CCS) Hardware Validation Group is responsible for ensuring the quality, reliability, and performance of next generation data center ASIC and SoC products spanning a diverse portfolio that includes cloud infrastructure, AI accelerators, network processors, NICs, custom ASICs, SSD controllers, CXL devices, and domain specific accelerators. The team owns end to end hardware validation, working across the product lifecycle from early silicon bring up through system level qualification. Our scope includes functional hardware validation, electrical characterization, high speed SERDES validation, and system/platform validation, all executed in advanced, fully instrumented hardware labs. The group validates complex, high-performance silicon and platforms across a wide range of critical technologies and interfaces, including Memory Subsystems (DDR, HBM, memory controllers), High Speed Interconnects (PCIe, Ethernet, CPRI, PAM4/NRZ), D2D interconnects, Storage, and IO (Flash and NVME, SSD controllers, USB) and System and Platform testing. What You Can Expect We are seeking an experienced Signal Integrity / Power Integrity (SI/PI) Engineer to drive the design, analysis, and validation of high‑speed electronic systems. The successful candidate will play a critical role in ensuring robust signal and power performance across silicon, package, PCB, and system levels for next‑generation products. In this role, you will partner closely with architecture, silicon, package, board design, validation, and manufacturing teams to influence hardware decisions, identify risks early in the design cycle, and ensure compliance with performance, reliability, and interoperability requirements.

Requirements

Bachelor’s degree in Computer Science, Electrical Engineering or related fields and 10-15 years of related professional experience OR Master’s degree in Computer Science, Electrical Engineering or related fields with 5-10 years of experience.
Proven record of technical leadership and ownership across multiple product generations, driving SI/PI excellence from early architecture through production.
Deep expertise in high‑speed signal integrity analysis and design, including transmission line theory, channel modeling, and loss/jitter/noise mechanisms.
Extensive hands‑on experience with advanced high‑speed interfaces, such as DDR4 / DDR5 / LPDDR, HBM, PCIe Gen4 / Gen5 / Gen6, Ethernet (25G/50G/100G+ NRZ and PAM4 SerDes), high‑speed chip‑to‑chip links
Strong understanding of package, PCB, and connector effects on end‑to‑end channel performance.
Expertise in pre‑layout and post‑layout SI simulations, timing margin analysis, eye‑diagram analysis, jitter decomposition, and compliance validation.
Deep knowledge of power distribution network (PDN) design, including on‑die, package, and board‑level power delivery.
Expertise in AC and transient PI analysis, impedance target formulation, decoupling strategies, VR design, and noise mitigation.
Practical experience analyzing and resolving simultaneous switching noise (SSN), ground bounce, and rail collapse issues.
Expert‑level proficiency with industry‑standard SI/PI tools, such as Cadence Sigrity (PowerSI, SystemSI, OptimizePI), Siemens HyperLynx, Keysight ADS / EMPro, Ansys HFSS / SIwave, Equivalent extraction and EM simulation tools.
Experience collaborating with memory, SerDes, PHY, silicon, packaging, thermal, mechanical, and validation teams to resolve cross‑domain issues.
Hands‑on experience supporting board bring‑up, lab debug, and post‑silicon validation, correlating simulation results with lab measurements.
Ability to act as a technical authority and decision maker for SI/PI architecture and design trade‑offs across programs.
Strong communication skills, capable of clearly presenting technical risks, trade‑offs, and recommendations to engineering leadership and executive stakeholders.

Responsibilities

Lead SI and PI analysis for high‑speed digital interfaces, from early architecture definition through post‑silicon validation and production enablement.
Perform pre‑layout and post‑layout signal integrity analysis, including channel modeling, eye‑diagram analysis, jitter decomposition, timing margin analysis, and compliance assessments.
Design and analyze power distribution networks (PDN) across die, package, and PCB, including AC impedance analysis, transient simulations, decoupling strategies, and noise mitigation.
Support and optimize high‑speed interfaces such as DDR4/DDR5, HBM, PCIe Gen4/Gen5/Gen6, Ethernet (NRZ and PAM4), and other SerDes‑based links.
Develop and enforce SI/PI guidelines, methodologies, and sign‑off criteria to ensure consistent design quality across multiple programs.
Collaborate with package, PCB, and connector teams to evaluate layout trade‑offs, stack‑ups, materials, and routing strategies impacting end‑to-end channel performance.
Correlate simulation results with lab measurements, supporting board bring‑up, debug, and post‑silicon characterization using oscilloscopes, TDRs, VNAs, and other lab tools.
Identify and drive resolution for cross‑domain issues involving signal integrity, power integrity, timing, EMI/EMC, and thermal interactions.
Provide technical leadership through design reviews, mentoring engineers and influencing architectural decisions with data‑driven recommendations.
Support customer engagements, field issues, or escalations requiring deep SI/PI expertise.