Hardware & Silicon Validation Senior Staff Engineer

Marvell Technology•Santa Clara, CA

About The Position

About Marvell Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact The Custom Cloud Solutions (CCS) Hardware Validation Group is responsible for ensuring the quality, reliability, and performance of next generation data center ASIC and SoC products spanning a diverse portfolio that includes cloud infrastructure, AI accelerators, network processors, NICs, custom ASICs, SSD controllers, CXL devices, and domain specific accelerators. The team owns end to end hardware validation, working across the product lifecycle from early silicon bring up through system level qualification. Our scope includes functional hardware validation, electrical characterization, high speed SERDES validation, and system/platform validation, all executed in advanced, fully instrumented hardware labs. The group validates complex, high-performance silicon and platforms across a wide range of critical technologies and interfaces, including Memory Subsystems (DDR, HBM, memory controllers), High Speed Interconnects (PCIe, Ethernet, CPRI, PAM4/NRZ), D2D interconnects, Storage, and IO (Flash and NVME, SSD controllers, USB) and System and Platform testing. What You Can Expect • Own the end‑to‑end validation strategy for DDR and HBM subsystems, from pre‑silicon planning through post‑silicon bring‑up, characterization, and production readiness. • Define validation scope, coverage metrics, and test methodologies for memory controllers, PHYs, and full memory subsystems, ensuring compliance with JEDEC specifications and internal quality standards. • Lead post‑silicon bring‑up and debug of complex memory systems, driving root‑cause analysis across silicon, firmware, signal integrity, power integrity, and test infrastructure domains. • Serve as the primary technical authority for DDR and HBM validation, providing guidance on architecture trade‑offs, risk mitigation, and design optimization. • Drive cross‑functional collaboration with architecture, RTL, PHY, SI/PI, firmware, system validation, and product engineering teams to resolve issues and influence design improvements. • Lead development and execution of stress, corner‑case, performance, and RAS testing across PVT conditions to ensure long‑term reliability and robustness. • Partner with firmware and software teams to define and validate training algorithms, diagnostics, error handling, and recovery mechanisms. • Present technical findings, risk assessments, and validation status to engineering leadership and program stakeholders, enabling data‑driven decision making. • Actively influence best practices in validation methodology, automation, and lab infrastructure, helping scale validation efficiency for future silicon generations. • Support customer‑facing debug and escalations when required, providing expert‑level analysis and guidance on memory‑related issues.

Requirements

Bachelor’s degree in Computer Science, Electrical Engineering, or a related field with 5–10 years of relevant industry experience; or Master’s degree and/or PhD in Computer Science, Electrical Engineering, or a related discipline with 3–5 years of professional experience.
Deep hands‑on expertise in DDR memory technologies including DDR4, DDR5 and LPDDR4/5, covering protocol, timing, training, power management, and system‑level behavior.
Expert understanding of memory subsystem architecture, including controller, PHY, interconnect, training algorithms, error handling (ECC), and RAS features.
Extensive experience validating JEDEC memory standards, interpreting specifications, and ensuring compliance across process, voltage, temperature (PVT) corners.
Demonstrated expertise in post‑silicon bring‑up, validation, stress testing, and debug of memory subsystems at block, subsystem, and full‑chip levels.
Hands‑on experience with high‑speed lab equipment, including oscilloscopes, logic analyzers, protocol analyzers, and memory test platforms.
Proficiency in C/C++ for embedded or bare‑metal firmware development to support memory bring‑up, training, diagnostics, and stress testing.
Strong experience developing Python‑based automation frameworks for functional, regression, stress, and manufacturing validation.
Experience leading validation strategy and test planning for DDR and HBM subsystems, including coverage definition and execution ownership.
Excellent written and verbal communication skills, with the ability to present technical findings clearly to engineering leadership and executive stakeholders.

Nice To Haves

Background in HBM (HBM2 / HBM2E / HBM3 / HBM4 / HBM4E) architecture and validation, including stack integration, memory controllers, PHY interaction, bring‑up, and performance characterization is strongly preferred.
Hands-on wafer probe experience operating wafer probers, probe cards and automated test equipment(ATE) along with understanding of wafer-level test flow is preferred.
Strong debugging skills using JTAG, boundary scan and trace tools is preferred.

Responsibilities

Own the end‑to‑end validation strategy for DDR and HBM subsystems, from pre‑silicon planning through post‑silicon bring‑up, characterization, and production readiness.
Define validation scope, coverage metrics, and test methodologies for memory controllers, PHYs, and full memory subsystems, ensuring compliance with JEDEC specifications and internal quality standards.
Lead post‑silicon bring‑up and debug of complex memory systems, driving root‑cause analysis across silicon, firmware, signal integrity, power integrity, and test infrastructure domains.
Serve as the primary technical authority for DDR and HBM validation, providing guidance on architecture trade‑offs, risk mitigation, and design optimization.
Drive cross‑functional collaboration with architecture, RTL, PHY, SI/PI, firmware, system validation, and product engineering teams to resolve issues and influence design improvements.
Lead development and execution of stress, corner‑case, performance, and RAS testing across PVT conditions to ensure long‑term reliability and robustness.
Partner with firmware and software teams to define and validate training algorithms, diagnostics, error handling, and recovery mechanisms.
Present technical findings, risk assessments, and validation status to engineering leadership and program stakeholders, enabling data‑driven decision making.
Actively influence best practices in validation methodology, automation, and lab infrastructure, helping scale validation efficiency for future silicon generations.
Support customer‑facing debug and escalations when required, providing expert‑level analysis and guidance on memory‑related issues.