Hardware & Silicon Validation Director
About The Position
Marvell's Central System Engineering (CSE) group is part of Central Engineering (CE), the engine that powers every Business Unit at Marvell. CSE is an independent function within CE responsible for validating all Marvell High-Speed PHY(Serdes/D2D) IPs, in the lab environment and supporting all Marvell Business Units for fast and smooth SoC production. The team develops data communication system hardware infrastructure and large-scale automation to deliver the highest quality PHY IP and analog macros across Marvell's product portfolio, spanning Switch, Automotive, Storage, Optics, and more. We are seeking a highly motivated and experienced Validation Director to lead the silicon validation team for our High Speed PHY products. This is a critical leadership role responsible for driving validation strategy, execution, and team development across multiple generations of cutting-edge PHY products operating at 100G+ per lane.
Requirements
- BS/MS degree in Electrical Engineering or related technical field.
- 15+ years of experience in semiconductor silicon validation, hardware design, or related disciplines.
- 5+ years of people management experience, with a demonstrated track record of building and leading high-performing engineering teams.
- Deep technical expertise in high-speed PHY validation, including SerDes, Ethernet transceivers (10G–800G), and/or PCIe.
- Hands-on experience with post-silicon bring-up, debug, and characterization of complex mixed-signal ICs.
- Strong working knowledge of lab instrumentation including high-speed oscilloscopes, BERTs, spectrum analyzers, signal generators, and network analyzers.
- Proficiency in scripting and test automation (Python, MATLAB, or equivalent).
- Excellent verbal and written communication skills; ability to present complex technical topics clearly to executive leadership.
Nice To Haves
- MS or PhD in Electrical Engineering with focus on high-speed communications or mixed-signal design.
- Experience with IEEE 802.3 Ethernet compliance testing (100G, 400G, 800G) and/or PCIe Gen 5/6 compliance and interoperability.
- Familiarity with signal integrity analysis, eye diagram characterization, and jitter analysis methodologies.
- Experience managing geographically distributed teams across multiple sites.
- Prior experience in a Director-level role within a semiconductor company.
- Knowledge of DSP algorithms and firmware used in high-speed transceiver products.
Responsibilities
- Lead and manage a multi-disciplinary team of silicon validation engineers responsible for post-silicon bring-up, characterization, and compliance testing of high-speed PHY products (Ethernet, PCIe, SerDes).
- Define and own the overall validation strategy, methodology, and test plans for High Speed PHY products from A0 silicon through production release.
- Drive bring-up, debug, and characterization of analog front-end (AFE), ADC/DAC, PLL/DLL, CDR, and SerDes IP blocks at block and system levels.
- Oversee compliance and interoperability testing against industry standards including IEEE 802.3, PCIe Gen 5/6, and other relevant specifications.
- Partner closely with analog/digital design, DSP, firmware, system engineering, and application engineering teams to resolve silicon issues and drive product quality.
- Develop and implement lab automation infrastructure and test frameworks to enable large-scale, high-throughput characterization across PVT corners.
- Own resource planning, headcount management, and budget for the validation organization; work with senior leadership to prioritize programs and allocate resources effectively.
- Establish and maintain strong cross-functional relationships with Business Unit leaders, marketing, and program management to align validation milestones with product schedules.
- Provide technical mentorship and career development guidance to team members; build a high-performing, inclusive team culture.
- Engage with key customers and field application engineers to support customer bring-up, debug, and issue resolution.
- Contribute to the definition of next-generation PHY products by providing validation insights and feedback to design and architecture teams.
Benefits
- employee stock purchase plan with a 2-year look back
- family support programs to help balance work and home life
- robust mental health resources to prioritize emotional well-being
- recognition and service awards to celebrate contributions and milestones
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What This Job Offers
Job Type
Full-time
Career Level
Director
