Hardware Research Analyst

SemiAnalysis•Hillsboro, OR

9h•Hybrid

About The Position

We are seeking a Hardware Research Analyst to join our team in Hillsboro, OR, producing published technical analysis of leading-edge AI and datacenter hardware. You will take products through teardown in our lab and turn physical evidence into the research the industry reads first. Each product becomes a body of published work, and you write it: the most important stories of the teardown told in technical prose, backed by the complete data and analysis. The role rewards the analyst temperament. The strongest people in this work follow the industry in real time, keep up with conferences and papers, work their networks constantly, and want their name on research that holds up in front of the people who built the product. We have several open roles in the lab; apply to the closest fit and we'll route you.

Requirements

We are hiring at all experience levels: 2+ years in hardware or silicon engineering, system architecture, or technical industry analysis is preferred; exceptional candidates at any level are encouraged to apply
Genuine exposure to leading-edge parts
Broad functional knowledge of AI and datacenter hardware: GPUs, CPUs, accelerators, memory, networking, power delivery, and packaging, from die to rack
Strong technical writing with work you can show: published articles, papers, or substantial long-form technical documents
An established research habit: you already track this industry through conferences, papers, and product launches
Ability to reason across layers, from device and circuit through architecture, system, workload, and cost
Hands-on experience with, or strong aptitude for, semiconductor sample preparation and analytical tools such as precision polishing, FIB, SEM, and related electron-beam, X-ray, and compositional methods

Nice To Haves

Direct engineering experience on leading-edge silicon or systems: design, architecture, validation, silicon debug, failure analysis, or manufacturing
Interpreting micrographs, die imagery, and electrical measurements to infer design and process characteristics
Cost modeling: die cost, bill of materials, and total cost of ownership
Advanced packaging knowledge (2.5D/3D integration, hybrid bonding, HBM, co-packaged optics)
Python for data analysis and engineering tasks (image analysis, data pipelines, automation)
A public technical writing track record or existing industry following
Conference participation as attendee or presenter (ISSCC, IEDM, VLSI, Hot Chips, ISTFA, PAINE, ECTC, OCP)
Strong professional network of experts

Responsibilities

Publish a complete body of work for each product, from the most important stories of the teardown through the full data and analysis
Own products end to end: acquisition planning, teardown strategy, lab analysis, interpretation, and publication
Analyze hardware at every level: silicon process and die architecture, packaging, memory, power delivery, interconnect, board and system design, and cost
Set the analytical plan for each teardown; operate the toolchain and direct more specialized work as needed
Maintain contemporaneous coverage of the industry through conferences, papers, patents, and supply chain signals, and bring it into every report
Build and work an expert network across the supply chain to test and sharpen conclusions
Translate physical evidence into architectural intent, cost structure, and roadmap implications
Contribute to the growth and expansion of the lab's capabilities and output; bring your unique skills to a strong and expansive team