Hardware Machine Learning Engineer

IMC•New York, NY

4d•$200,000 - $225,000

About The Position

The Hardware Machine Learning Engineer will help deploy machine learning directly onto custom hardware. The role offers the opportunity to architect solutions from the ground up, influence technical research direction, and deliver work in a demanding computing environment. The company builds its own hardware, software, and infrastructure, allowing engineers to address bottlenecks without relying on vendors or restricted abstraction layers. Candidates from a range of research and engineering backgrounds are welcome; trading experience is a bonus, not a prerequisite. The engineer will co-design machine learning models with traders, quantitative researchers, software engineers, and hardware engineers, incorporating latency, resource, and numerical-precision constraints into model and hardware decisions. The role also involves implementing, verifying, and deploying inference solutions from proof of concept through production, and evaluating research in neural architecture search, machine learning systems, and quantization for practical improvements.

Requirements

Solid understanding of hardware constraints and design trade-offs, such as pipelining, resource utilization, and fixed-point arithmetic, that affect how machine learning models are mapped efficiently onto FPGAs or custom ASICs.
Experience with hardware fundamentals through VHDL/SystemVerilog development, HLS tools, or machine-learning-to-hardware frameworks such as hls4ml, FINN, or Vitis AI.
Understanding of machine learning fundamentals, including neural network architectures, inference optimization, quantization techniques, and frameworks such as PyTorch or TensorFlow.
Proficiency in Python, C++, or similar languages for tooling, testing, and simulation.
Strong communication skills and ability to collaborate across disciplines with technical and non-technical teams.

Nice To Haves

Exposure to machine learning compiler infrastructure such as MLIR, TVM, XLA, or similar tools for lowering and optimizing models for hardware targets.
Background in latency-sensitive or resource-constrained systems, including high-frequency trading, particle physics data acquisition, real-time signal processing, or similar domains.
Familiarity with functional verification methodologies, for example SystemVerilog, UVM, or Cocotb.
Advanced degree (MS or PhD) in EE, CS, Physics, or a related field, or equivalent depth through industry or research experience.

Responsibilities

Architect and co-design machine learning models with traders, quantitative researchers, and software engineers, treating hardware constraints such as latency budgets, resource limits, and numerical precision as first-class design inputs.
Shape the custom hardware roadmap by translating machine learning model requirements into concrete architectural decisions.
Work hands-on with hardware engineers to implement, verify, and deploy machine learning inference solutions from proof of concept through production.
Track and evaluate emerging research in neural architecture search, machine learning systems, and quantization methods, and determine what can produce measurable improvements in the systems.