Hardware Lab Manager

Cspeed•Palo Alto, CA

1d•Onsite

About The Position

CspeedIO is a stealth startup backed by Sutter Hill Ventures and Atreides Capital - headquartered in Palo Alto, CA. Our executive team has a demonstrated track record of building and scaling category-defining semiconductor and infrastructure businesses at companies like Broadcom, Lumentum, Tesla, Apple, Samsung, Intel, and VMware. CspeedIO is developing next-generation optical semiconductor solutions for the AI infrastructure market, focused on enabling true “scale-up” architectures. Our mission is to replace traditional copper interconnects with advanced fiber-optic technologies that overcome the limitations of existing optics solutions and architectures. The Role The lab is where our product stops being a design and starts being real. You will own it — the physical lab and its expansion, the test and validation work that happens in it, and the boards that everything gets tested on. Almost every team here needs boards (CMOS bring-up vehicles, packaging test structures, optics characterization fixtures, systems validation boards) and this would roll up under you. The engineers who define requirements stay in their own lanes; you turn their requirements into hardware that works the first time. This is hands-on — schematics, layout review, and bench time during bring-up — and it is also leadership. You will build the lab team and lead senior technical ICs. Our near-term board focus is from evaluation through production, and you will own this too.

Requirements

10+ years in hardware engineering spanning board design and hardware test/validation, on products that shipped
Hands-on and current — you still capture schematics, review layout, and take your own measurements, and you want a role where that is expected
Board design depth — complex, high-layer-count mixed-signal boards from concept to working hardware in a professional EDA flow (Altium, Allegro, Xpedition, or equivalent), including ASIC and package bring-up vehicles
High-speed SI and power integrity expertise — multi-gigabit channel design at multi-gigabit PAM4 class rates and above, stackup and material trade-offs, via optimization, simulation-to-measurement correlation, and PDN design
Validation ownership — you have run a validation program through DVT and PVT, and you know the difference between a number and a defensible number
Lab leadership — you have built out or substantially expanded a hardware lab: equipment selection, capital justification, and the operational discipline that keeps it working
People leadership — you have led engineers and technicians, and can hold a discipline together across teams that do not report to you
Strong Python scripting and data analysis — you automate your own measurements and are comfortable with the statistics behind them
BS or MS in Electrical Engineering, or equivalent experience

Nice To Haves

Advanced packaging exposure: interposers, 2.5D/3D assemblies, die-to-die interfaces, and the test vehicles that qualify them
Familiarity with IEEE 802.3 electrical and optical compliance, module form factors, and host-side interoperability
Reliability and qualification exposure (HTOL, accelerated aging, environmental test), or experience bridging an R&D lab into production test
Startup experience, or otherwise a tolerance for building the process at the same time as the product

Responsibilities

Lead lab expansion: space planning, bench and rack layout, power, cooling, ESD control, and fiber and cable infrastructure
Own the capital equipment budget and roadmap — specify, justify, source, and bring up BERTs, high-bandwidth scopes, VNAs, optical spectrum and power measurement, thermal chambers, probe stations, and fixturing
Run lab operations: asset and calibration tracking, instrument scheduling, configuration control of test setups, and lab safety around high-power optical sources and high-current supplies
Own test and validation for our optical engines across EVT, DVT, and PVT — the validation plan, the test matrix, and the entry and exit criteria that gate each build phase
Ensure measurements are defensible: repeatability, calibration, de-embedding, stated uncertainty, and correlation between setups and between sites
Lead bring-up and debug of new hardware revisions, and drive failures to root cause across electrical, optical, thermal, firmware, and test-setup causes
Own the characterization reports and compliance evidence that go to customers and into program reviews
Be the single point of accountability for board requirements across CMOS, packaging, optics, and systems — running intake, pushing back on requirements that will not build, and setting the standards, libraries, and review process
Own the full flow: requirements, architecture, schematic capture, stackup and constraints, layout direction and review, fab and assembly, and bring-up — designing the boards that matter most yourself
Deliver ASIC and package bring-up vehicles: socketed and BGA test boards, interposer and package test structures, probe and debug access, and the power and clocking around them
Own SI and PI: stackup and material selection, via and breakout design, connector and package transitions, loss and crosstalk budgets, and PDN design for high-current digital and low-noise optical rails
Design de-embeddable high-speed characterization and compliance fixtures, and take the product boards from concept through production as the program matures
Manage external layout resources, fab houses, and assembly partners — quality, cost, turn time, yield, DFM and DFT
Own the automated test infrastructure and the results database, so runs are repeatable, versioned, and still interpretable months later
Build and lead the lab team — validation engineers, board designers, technicians, and contract resources — and coordinate lab capability with our global sites
Be the honest voice on schedule and on whether the hardware is actually ready